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TDA18271HD
Silicon Tuner IC
Rev. 04 -- 19 May 2009 Product data sheet
1. General description
The TDA18271HD is a Silicon Tuner IC designed mainly for terrestrial analog and digital TV reception. The TDA18271HD integrates the overall tuning function, including selectivity. The TDA18271HD is compatible with all analog and digital TV standards and delivers a low IF signal to a demodulator (for analog TV) and/or channel decoder (for digital TV). This specification is based on software version 3.4.
2. Features
I Fully integrated RF tracking filters for unwanted signal suppression I Fully integrated IF selectivity (no need for external SAW filters) I Worldwide multistandard terrestrial (all analog and digital worldwide terrestrial standards supported) I Integrated loop-through and slave tuner output for straightforward multi-Silicon Tuner application I Fully integrated oscillators with no external components I Alignment free I Integrated wide-band gain control I Single 3.3 V power supply I Low power consumption I Crystal oscillator output buffer (16 MHz) for single crystal applications I I2C-bus interface compatible with 3.3 V and 5 V microcontrollers I Three Standby modes I RoHS packaging
3. Applications
3.1 Target applications
I Hybrid (analog and digital TV) for PCTV, DVD-R and TV applications I Application optimization is described in application notes AN602, AN604 and AN605
NXP Semiconductors
TDA18271HD
Silicon Tuner IC
3.2 Key benefits
I The TDA18271HD is a Silicon Tuner targeting digital and analog TV applications. The aim is to match the performance of conventional Can tuners while reducing the size of the tuner function. Additionally, the following benefits are provided: N Easy on-board integration N Easy dual tuner configuration N Drastic size reduction of the tuner function and power consumption
4. Quick reference data
Table 1. fRF(STO) NFtun n P Vi(max) Quick reference data Conditions slave tuner output maximum gain 1 kHz and 10 kHz Min 45 Typ 5.5 -89 780 103 Max 864 Unit MHz dB dBc/Hz mW dBV RF frequency on pin STO tuner noise figure phase noise power dissipation maximum input voltage 1 dB gain compression, one analog TV signal at RF input (-5 dBm) image rejection digital sensitivity analog sensitivity DVB-T (64 QAM BER = 2.10-4
2 3); [1]
Symbol Parameter
image Sdig Sa
-
65 -82 58
-
dB dBm dBV
50 dB video SNR weighted 22 dBV (color loss)
[2]
[1] [2]
Measured with TDA10048HN channel decoder. Measured with TDA8295 IF modulator.
5. Ordering information
Table 2. Ordering information Package Name TDA18271HD/C2 Description Version SOT903-1 HLQFN64R plastic thermal enhanced low profile quad flat package; no leads; 64 terminals; resin based; body 9 x 9 x 1.6 mm Type number
TDA18271HD_4
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Silicon Tuner IC
6. Block diagram
AGC CONTROL DC-to-DC CONVERTER LC tracking filters ATTENUATORS AGC1 AGC2 RF AGC AGC DUAL TUNER PROTOCOL 46 47 28 19 RF polyphase filter DIGITAL CIRCUITRY IF polyphase mixer filter IF low-pass filter
LNA RF_IN 10
IF AGC 45
IFOUTN IFOUTP V_IFAGC FREEZE MASTERSYNC
STO LT FM_IN
15 13 8
TDA18271HD
CONTROL INTERFACE 32 AS 38 39
TEST SIGNAL GENERATOR CALIBRATION SYNTHESIZER 35 VT_CAL
DIVIDER crystal oscillator MAIN SYNTHESIZER 27 XTALN 24 CP_LO 22 21 VT_COARSE VCO
34 26 CP_CAL XTALP
SCL SDA
VT_FINE
001aag453
Fig 1.
Block diagram
TDA18271HD_4
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Silicon Tuner IC
7. Pinning information
7.1 Pinning
CAPREGFILTRF
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND 50
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND GND GND GND GND GND GND FM_IN VCC RF_IN GND CAPRFAGC LT GND STO VCC
1 2 3 4 5 6 7 8
49 48 47 46 45 44 43 42 41
GND
terminal 1 index area
VSYNC
GND V_IFAGC IFOUTP IFOUTN VCC GND CAPREG28 GND CAPREG18 SDA SCL GND GND VT_CAL CP_CAL VCC
TDA18271HD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AS
001aag454
(c) NXP B.V. 2009. All rights reserved.
40 39 38 37 36 35 34 33
MASTERSYNC
CAPFILTVCO
VT_COARSE
VT_FINE
GND
CP_LO
GND
XTALP
XTALN
FREEZE
XTOUT_MS
XTOUTP
CAPREGVCO
Transparent top view
Fig 2.
Pin configuration
7.2 Pin description
Table 3. Symbol GND FM_IN VCC RF_IN GND CAPRFAGC LT
TDA18271HD_4
Pin description Pin 1 to 7 8 9 10 11 12 13 Description ground unbalanced FM input 3.3 V supply voltage unbalanced RF (TV) input ground RF AGC filtering loop-through output
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Product data sheet
XTOUTN
VCC
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TDA18271HD
Silicon Tuner IC
Pin description ...continued Pin 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36, 37 38 39 40 41 42 43 44 45 46 47 48 to 50 51 52 53 to 64 Description ground slave tuner output 3.3 V supply voltage VCO supply decoupling 3.3 V supply voltage synchronization signal for dual tuner applications; leave open for single tuner applications VCO reference decoupling LO tuning voltage input LO tuning voltage input ground charge pump of the local synthesizer ground crystal oscillator input crystal oscillator input synchronization signal for multi tuner applications; leave open for single tuner applications XTOUT mode and master/slave selection crystal oscillator output buffer crystal oscillator output buffer I2C-bus address selection input 3.3 V supply voltage charge pump of the calibration synthesizer tuning voltage of the calibration synthesizer ground I2C-bus clock input I2C-bus data input/output internal regulator decoupling ground internal regulator decoupling ground 3.3 V supply voltage IF output IF output IF gain control input ground vertical synchronization input for analog applications; connect to ground for digital applications internal regulator decoupling ground
Table 3. Symbol GND STO VCC
CAPREGVCO VCC MASTERSYNC CAPFILTVCO VT_COARSE VT_FINE GND CP_LO GND XTALP XTALN FREEZE XTOUT_MS XTOUTP XTOUTN AS VCC CP_CAL VT_CAL GND SCL SDA CAPREG18 GND CAPREG28 GND VCC IFOUTN IFOUTP V_IFAGC GND VSYNC CAPREGFILTRF GND GND
exposed die ground
TDA18271HD_4
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TDA18271HD
Silicon Tuner IC
8. Functional description
The RF input signal is driven to a low-noise amplifier. It is then band-pass filtered, amplified and fed to the image rejection mixer. The mixer downconverts the RF signal to a low IF depending on the channel bandwidth. Standard IF filters are implemented for 1.5 MHz, 6 MHz, 7 MHz and 8 MHz channel bandwidths; see Table 43. The Silicon Tuner can be used either as TV receiver or FM radio receiver. The TDA18271HD requires a single 16 MHz crystal for clock generation. When bit XTOUT_ON = 1, a clock signal is available on pins XTOUTP and XTOUTN to drive a second tuner, a channel decoder or an IF demodulator (TDA8295) for analog TV reception and FM radio. Remark: Most recent video decoders from NXP Semiconductors include a low IF demodulation function.
8.1 TV and FM reception
The Silicon Tuner can be used in two modes, selectable via the I2C-bus:
* TV reception: the RF signal must be connected to pin RF_IN * FM reception: the RF signal must be connected to pin FM_IN or RF_IN
The RF_IN input pin can also be used for FM reception at the cost of software modification. The FM_IN input pin can only receive signals in the FM frequency range.
8.2 Master and slave operation
The TDA18271HD allows easy dual-tuner configuration. Each individual tuner has to be set either to Master mode or Slave mode by applying a specific DC voltage to the XTOUT_MS pin; see Table 4. This will decide whether the crystal oscillator part is used as negative impedance connected to the crystal part or as a current buffer.
Table 4. Master/slave selection Tuner type master slave Crystal oscillator function negative impedance presented to the crystal current input buffer
Voltage on pin XTOUT_MS 0 V to 0.1VCC 0.4VCC to 0.6VCC
In dual tuner applications:
* The first tuner is set to Master mode * The second tuner has to be set to Slave mode
In single tuner applications:
* The tuner must be set to Master mode
TDA18271HD_4
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Product data sheet
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Silicon Tuner IC
8.3 Tuner outputs
The tuner provides a slave tuner output (pin STO) and a loop-through output (pin LT). These outputs are used to transmit the antenna signal to other tuners. Each output has its own characteristics (see Table 58 and Table 59).
8.3.1 Loop-through output
The gain between the antenna connector and the loop-through pin (pin LT) equals 0 dB. This pin can be connected to any consumer electronic equipment.
8.3.2 Slave tuner output
In dual tuner applications the slave tuner output (pin STO) must be connected to the RF input of the slave tuner TDA18271HD. The gain between the antenna connector and the slave tuner output can change according to the input level. The slave tuner will automatically compensate for the gain change, using the MASTERSYNC and FREEZE signals.
8.4 Crystal input mode
The TDA18271HD requires a 16 MHz crystal reference. The chosen crystal must withstand at least 100 W drive level and an additional shunt capacitor with a typical value of 5.6 pF as shown in Figure 1 is also needed. The quartz references for which the performances are guaranteed are:
* * * *
NDK NX5032 Siward SX-5032 TXC 9C series Chungho Elcom HC49S profile
Clock reference:
* In Master mode, the clock reference must be provided by a 16 MHz crystal connected
between pins XTALP and XTALN of the master tuner
* In Slave mode, the clock reference must be provided by pins XTOUTP and XTOUTN
of the tuner in Master mode to pins XTALP and XTALN of the tuner in Slave mode
8.5 Crystal output mode
Pins XTOUTP and XTOUTN deliver a symmetrical sine waveform to drive the channel decoder and/or IF demodulator. The load on these outputs should be made similar to ensure optimum performances. If only one crystal output is used, the unused output should be loaded by an equivalent capacitance.
TDA18271HD_4
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9. Control interface
9.1 I2C-bus format, Write/Read mode
Remark: The I2C-bus read in the TDA18271HD must read the entire I2C-bus map, with required subaddress 00h. The number of bytes read is 16, or 39 in extended register mode; see Table 7. Reading write-only bits can return values that are different from the programmed values.
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Product data sheet Rev. 04 -- 19 May 2009
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Table 5. Name
I2C-bus format Byte name ID TM PL EP1 Sub address 00h 01h 02h 03h POWER_ LEVEL[8] DIS_ POWER_ LEVEL RF_BAND[2:0] SM FM_RFN EXTENDED _REG 0 SM_LT XTOUT_ON SM_XT 1 IR_GSTEP[2:0] AGCK_MODE[1:0] IF_LEVEL[2:0] 0 CAL_POST_DIV[7:0] CAL_DIV[22:16] CAL_DIV[15:8] CAL_DIV[7:0] IF_NOTCH 0 MAIN_POST_DIV[6:0] MAIN_DIV[22:16] MAIN_DIV[15:8] MAIN_DIV[7:0] EB1[7:3] CALVCO_ FORLON EB2[7:0] EB3[7:0] EB4[7:6] LO_FORCE SRCE EB5[7:0] EB6[7:0] EB4[4:0] AGC1_ ALWAYS_ MASTERN AGC1_ FIRSTN 0 Bit 7 1 0 1 POR LOCK TM_RANGE TM_ON POWER_LEVEL[7:0] RF_CAL_OK IR_CAL_OK BP_FILTER[2:0] 6 1 0 ID[6:0] TM_D[3:0] 5 0 4 0 3 0 AD[5:0] 2 MA[1:0] 1 0 R/W
Address byte 1 Address byte 2 ID byte Thermo byte Power level byte Easy prog byte 1
Easy prog byte 2 Easy prog byte 3 Easy prog byte 4 Easy prog byte 5 Cal post-divider byte Cal divider byte 1 Cal divider byte 2 Cal divider byte 3 Main post-divider byte Main divider byte 1 Main divider byte 2 Main divider byte 3 Extended byte 1
EP2 EP3 EP4 EP5 CPD CD1 CD2 CD3 MPD MD1 MD2 MD3 EB1
04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h
GAIN_TAPER[4:0] STD[2:0] CAL_MODE[1:0] IR_MEAS[2:0]
TDA18271HD
Extended byte 2 Extended byte 3 Extended byte 4 Extended byte 5 Extended byte 6
EB2 EB3 EB4 EB5 EB6
11h 12h 13h 14h 15h
Silicon Tuner IC
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Table 5. Name Extended byte 7 I2C-bus format ...continued Byte name EB7 Sub address 16h Bit 7 EB7[7:6] 6 5 CAL_ FORCE SRCE EB8[6:4] EB8[3] EB9[7:0] EB10[7:6] EB11[7:0] EB12[7:6] EB13[7] PD_AGC1_ DET RFC_K[2:0] EB15[7:4] EB16[7:0] EB17[7:0] AGC1_ LOOP_OFF EB20[7:6] AGC2_ LOOP_OFF EB22[7] RF_TOP[2:0] EB23[7:3] FORCE_ LOCK EB21[6:2] IF_TOP[3:0] FORCELP_ FC2_EN LP_FC EB23[0] EB18[6:2] EB19[7:0] EB20[4:0] AGC2_GAIN[1:0] AGC1_GAIN[1:0] PD_AGC2_ DET RFC_M[1:0] RFC_CPROG[7:0] EB15[3:0] EB12[3:0] EB13[1:0] CID_GAIN[5:0] 4 3 2 EB7[4:0] 1 0
Product data sheet Rev. 04 -- 19 May 2009
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Extended byte 8 Extended byte 9 Extended byte 10 Extended byte 11 Extended byte 12 Extended byte 13 Extended byte 14 Extended byte 15 Extended byte 16 Extended byte 17 Extended byte 18 Extended byte 19 Extended byte 20 Extended byte 21 Extended byte 22 Extended byte 23
EB8 EB9 EB10 EB11 EB12 EB13 EB14 EB15 EB16 EB17 EB18 EB19 EB20 EB21 EB22 EB23
17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
CID_ALARM
EB8[2:0]
TDA18271HD
Silicon Tuner IC
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9.2 I2C-bus at Power-On Reset
Table 6. Name Address byte 1 Address byte 2 ID byte Thermo byte Power level byte Easy prog byte 1 Easy prog byte 2 Easy prog byte 3 Easy prog byte 4 Easy prog byte 5 Cal post-divider byte Cal divider byte 1 Cal divider byte 2 Cal divider byte 3 Main post-divider byte Main divider byte 1 Main divider byte 2 Main divider byte 3 Extended byte 1 Extended byte 2 Extended byte 3 Extended byte 4 Extended byte 5 Extended byte 6 Extended byte 7 Extended byte 8 Extended byte 9 Extended byte 10 Extended byte 11 Extended byte 12 Extended byte 13 Extended byte 14 Extended byte 15 Extended byte 16 Extended byte 17 Extended byte 18 Extended byte 19 Extended byte 20 I2C-bus at Power-On Reset Byte ID TM PL EP1 EP2 EP3 EP4 EP5 CPD CD1 CD2 CD3 MPD MD1 MD2 MD3 EB1 EB2 EB3 EB4 EB5 EB6 EB7 EB8 EB9 EB10 EB11 EB12 EB13 EB14 EB15 EB16 EB17 EB18 EB19 EB20 Subaddress 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 7[1] 1 X 1 1 X X 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 X 1 0 1 0 1 0 0 0 0 1 6[1] 1 X 0 0 X 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 0 X 0 0 1 0 0 0 0 0 0 0 5[1] 0 AD[5] 0 0 X 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 X 0 0 0 0 0 0 0 0 0 0 4[1] 0 AD[4] 0 0 X 0 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 X 0 0 0 0 0 X X 0 X X 3[1] 0 AD[3] 0 X X 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X 0 X 0 0 0 0 X X X 0 X X 2[1] MA[1] AD[2] 1 X X 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 X 1 1 0 0 X X X 0 X X 1[1] MA[0] AD[1] 0 X X 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 X 1 1 1 0 X 0 X 0 0 X 0[1] X AD[0] 0 X X 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 X 0 1 0 0 X 0 X 0 0 X
TDA18271HD_4
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Table 6. Name
I2C-bus at Power-On Reset ...continued Byte EB21 EB22 EB23 Subaddress 24h 25h 26h 7[1] 0 0 1 6[1] 0 1 0 5[1] 1 0 1 4[1] 1 0 1 3[1] 0 1 0 2[1] 0 0 0 1[1] 1 0 0 0[1] 1 0 0
Extended byte 21 Extended byte 22 Extended byte 23
[1]
X indicates a bit not changed on reset.
9.3 Description of symbols used in I2C-bus format table
Table 7. I2C-bus register bits explanation Symbol MA[1:0] AD[5:0] Data bytes 00h 01h ID TM ID[6:0] POR LOCK TM_RANGE TM_ON TM_D[3:0] 02h 03h PL EP1 POWER_LEVEL[7:0] POWER_LEVEL[8] DIS_POWER_LEVEL RF_CAL_OK IR_CAL_OK BP_FILTER[2:0] 04h 05h EP2 EP3 RF_BAND[2:0] GAIN_TAPER[4:0] SM SM_LT SM_XT AGCK_MODE[1:0] STD[2:0] 06h EP4 FM_RFN XTOUT_ON IF_LEVEL[2:0] CAL_MODE[1:0] 07h EP5 EXTENDED_REG IR_GSTEP[2:0] IR_MEAS[2:0]
TDA18271HD_4
Address Byte
Description programmable address bits programmable address bits of the first programming byte chip identification number Power-On Reset bit indicates that the main synthesizer is locked to the programmed frequency range selection bit for the internal die sensor enables die temperature measurement data from die temperature measurement (read only) Power level indicator value (read only) disables the power-on level function indicates that the RF tracking filter calibration procedure has been successful indicates that the complete image rejection calibration procedure has been successful RF band-pass filter selection RF tracking filter band selection gain taper value Sleep mode, Standby modes
Reference Table 8 Table 9 Table 10 Table 11
Table 12 Table 13
Table 14 Table 15
defines the standard defines the standard selects which input is fed to RF filter provides the 16 MHz crystal reference on the XTOUTP and XTOUTN pins IF output level selection calibration mode selection enables the extended register addressing gain step for image rejection calibration image rejection measurement frequency range
(c) NXP B.V. 2009. All rights reserved.
Table 18
Table 19
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Silicon Tuner IC
Table 7. 08h 09h 0Ah 0Bh 0Ch
I2C-bus register bits explanation ...continued Symbol CAL_POST_DIV[7:0] CAL_DIV[22:16] CAL_DIV[15:8] CAL_DIV[7:0] IF_NOTCH adds a DC notch in IF for a better adjacent channels rejection; depends on standards LO synthesizer main divider bits Table 22 Description calibration synthesizer post-divider calibration synthesizer main divider bits Reference Table 20 Table 21 CPD CD1 CD2 CD3 MPD
Address Byte
MAIN_POST_DIV[6:0] LO synthesizer post-divider bits 0Dh 0Eh 0Fh 10h MD1 MD2 MD3 EB1 MAIN_DIV[22:16] MAIN_DIV[15:8] MAIN_DIV[7:0] CALVCO_FORLON AGC1_ALWAYS_ MASTERN AGC1_FIRSTN 13h 16h 17h 19h 1Bh 1Ch 1Dh 21h 23h 24h 25h 26h EB4 EB7 EB8 LO_FORCESRCE CAL_FORCESRCE CID_ALARM determines which VCO is used during Normal mode operations enables AGC1 normal operation whatever the tuner type (master or slave) determines which AGC (1 or 2) will be detected when detectors 1 and 2 are up forces the main PLL charge pump to source current to the main PLL loop filter forces the calibration PLL charge pump to source current to the calibration PLL loop filter indicates that signal sensed by the power detector used during calibrations is out of range calibration power detector output power-down of AGC1 detector power-down of AGC2 detector parameter used during the RF tracking filter calibration parameter used during the RF tracking filter calibration tuning word of the RF tracking filters turns off the AGC1 loop AGC1 gain forces the internal PLLs lock indicator to logic 1 turns off the AGC2 loop AGC2 gain Take-Over Point (TOP) of the RF AGC, detection in RF TOP of the RF AGC, detection in IF FM filter selection Table 24 Table 23
Extended bytes
EB10 CID_GAIN[5:0] EB12 PD_AGC1_DET PD_AGC2_DET EB13 RFC_K[2:0] RFC_M[1:0] EB14 RFC_CPROG[7:0] EB18 AGC1_LOOP_OFF AGC1_GAIN[1:0] EB20 FORCE_LOCK EB21 AGC2_LOOP_OFF AGC2_GAIN[1:0] EB22 RF_TOP[2:0] IF_TOP[3:0] EB23 FORCELP_FC2_EN LP_FC
9.3.1 I2C-bus address selection
The programmable module address bits MA[1:0] allow up to four tuners to be addressed in one system. Bits MA1 and MA0 are programmed by a specific voltage (VAS) applied to pin AS. The relationship between the status of bits MA[1:0] and the voltage applied to pin AS is shown in Table 8.
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Table 8. Address byte 1 bit description Legend: * power-on reset value. Bit 7 to 3 2 to 1 Symbol MA[1:0] Access R/W R/W 00 01 10 11 0 R/W R/W 0 1 Table 9. Address byte 2 bit description Legend: * power-on reset value. Bit 7 to 6 5 to 0 Symbol AD[5:0] Access R/W R/W Value 00 Description must be set to 00 programmable address bits of the first programming byte Value 1 1000* Description must be set to 1 1000 programmable address bits VAS = 0 V to 0.1 x VCC VAS = 0.2 x VCC to 0.3 x VCC VAS = 0.4 x VCC to 0.6 x VCC VAS = 0.9 x VCC to VCC write mode read mode
9.3.2 Description of chip ID byte
Table 10. ID - identification byte (subaddress 00h) bit description Legend: * power-on reset value. Bit 7 6 to 0 Symbol ID[6:0] Access R R Value 1* 000 0100* Description must be 1 TDA18271HD/C2 identification number
9.3.3 Description of temperature sensor byte
The temperature sensor is not available in Device-off mode, as it requires a 16 MHz clock to operate.
Table 11. TM - Thermo byte (subaddress 01h) bit description Legend: * power-on reset value. Bit 7 Symbol POR Access Value Description R 1* 0 6 LOCK R 1 0* 5 TM_RANGE R/W 1 0* 4 TM_ON R/W R 1 0* 3 to 0 TM_D[3:0]
TDA18271HD_4
power supply falls below the power-on reset level and is reset after a read operation ending with a stop condition power supply is above the power-on reset level main synthesizer is locked to the programmed frequency main synthesizer is not locked to the programmed frequency temperature range selection for the internal die sensor (see Table 52) 92 C to 122 C 60 C to 90 C enables die temperature measurement (see Table 52) disables die temperature measurement (see Table 52)
XXXX data from die temperature measurement (see Table 52)
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9.3.4 Description of power level byte (read mode)
There are 9 power level bits sent in power level bytes 2 and 3. They indicate the composite voltage gain of the LNA, the loaded attenuator voltage gains, and the level at the input of the RF AGC.
Table 12. PL - Power level (address 02h and 03h) bit description Legend: * power-on reset value. Address Register Bit 03h 02h EP1 PL 7 7 Symbol POWER_LEVEL[8] POWER_LEVEL[7] 00 01 10 11 6 to 5 POWER_LEVEL[6:5] R Access Value R Description AGC2 gain, attenuator voltage gain including load, the attenuator load is 50 (allows the maximum gain of -6 dB) -15 dB -12 dB -9 dB -6 dB AGC1 gain, LNA voltage gain, the LNA voltage gain assumes a 75 source impedance and a low output impedance 00 01 10 11 4 to 0 POWER_LEVEL[4:0] R 0 0000 0 0001 ... 1 1110 1 1111 6 dB 9 dB 12 dB 15 dB sensed level at the input of the RF AGC, detector slope is -1 dB/step 103 dBV (RMS value) 102 dBV (RMS value) ... 73 dBV (RMS value) 72 dBV (RMS value)
9.3.5 Description of Easy prog byte 1
Table 13. EP1 - Easy prog byte 1 (subaddress 03h) bit description Legend: * power-on reset value. Bit 7 6 5 4 Symbol POWER_LEVEL[8] DIS_POWER_LEVEL RF_CAL_OK Access Value Description R R/W R/W R/W 1* 0 0* see Table 12 power level disabled power level enabled must be set to 0 RF tracking filter calibration procedure (see Section 9.4.9); updated each time the procedure is started 1 0* successful not successful
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Table 13. EP1 - Easy prog byte 1 (subaddress 03h) bit description ...continued Legend: * power-on reset value. Bit 3 Symbol IR_CAL_OK Access Value Description R/W 1 0* 2 to 0 BP_FILTER[2:0] R/W 110* complete image rejection calibration procedure (see Section 9.4.4); can only be reset with POR successful not successful RF band-pass filter selection (see Table 44)
9.3.6 Description of Easy prog byte 2
Table 14. EP2 - Easy prog byte 2 (subaddress 04h) bit description Legend: * power-on reset value. Bit Symbol Access Value R/W R/W 1 1111* 0 0000 110* Description RF tracking filter band selection (see Table 45) gain taper value (see Table 49) minimum attenuation maximum attenuation 7 to 5 RF_BAND[2:0] 4 to 0 GAIN_TAPER[4:0]
9.3.7 Description of Easy prog byte 3
The TDA18271HD has three different Standby modes. Two Standby modes are dedicated to special application demands; the third Standby mode is called `device-off'. It represents the smallest achievable power consumption.
Table 15. EP3 - Easy prog byte 3 (subaddress 05h) bit description Legend: * power-on reset value. Bit 7 to 5 4 to 3 2 to 0 Symbol SM, SM_LT, SM_XT STD[2:0] Power modes Circuit SM_LT SM_XT LoopSlavethrough tuner output on on on on Crystal oscillator on on Normal mode Standby mode with crystal oscillator, slave-tuner output and loop-through output on Standby mode with only crystal oscillator and its output buffer on Device-off mode Mode[1] Access R/W Value 100 10010* Description Power modes Table 16 defines the standard description of standards (see Table 43)
AGCK_MODE[1:0] R/W R/W
Table 16. Bit SM
0 1
0 0
0 0
1 1
[1]
1 1
0 1
off off
off off
on off
In all modes, the I2C-bus interface remains active. All other bit settings are invalid.
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AGC modes AGC_MODE[1:0] EP3[4:3][1] 1 0 1 1 1 1 Reference signal internal VSYNC internal
Table 17. Standard FM radio
Analog TV standards Digital TV standards
[1]
Depending on the programmed AGC_MODE, AGC1 can be synchronous with either VSYNC or an internal 16 MHz signal; for analog reception, when no synchronization signal is available for VSYNC pin, the internal reference may be used.
9.3.8 Description of Easy prog byte 4
Table 18. EP4 - Easy prog byte 4 (subaddress 06h) bit description Legend: * power-on reset value. Bit 7 Symbol FM_RFN Access Value Description R/W 1 0* 6 5 XTOUT_ON R/W R/W R/W 000* 001 010 011 100 101 110 111 1 to 0 CAL_MODE[1:0] R/W 00* 01 10 11 1* 0 1* 4 to 2 IF_LEVEL[2:0] selection which input is fed to RF filter FM input (RF LNA on; FM LNA on) RF input (RF LNA on; FM LNA off) 16 MHz on pins XTOUT not 16 MHz on pins XTOUT must be set to logic 1 IF output level selection and attenuation with regard to 2 V (p-p) 2 V (p-p); 0 dB 1.25 V (p-p); 4 dB 1 V (p-p); 6 dB 0.8 V (p-p); 8 dB not used not used 0.6 V (p-p); 10.4 dB 0.5 V (p-p); 12 dB calibration mode selection no calibration (Normal mode) Power detection mode image rejection calibration (IRCAL) mode RF tracking filter calibration (RFCAL) mode
All calibrations require a precise set of sequential operations, therefore it is mandatory to follow the flowcharts described in Section 9.4. The TDA18271HD has two calibration modes: one for the image rejection calibration and one for the RF tracking filter calibration. The image rejection calibration optimizes tunable parameters inside the mixer using a set of internal measurements to ensure a 65 dB typical value of image rejection. The internal signal used during this phase is generated by the PLL calibration (CAL PLL).
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The RF tracking filters central frequency can be adjusted with the tuning word RFC_CPROG. The RF tracking filter calibration (RFCAL) uses an internal tone at the input of the tracking filters (generated by CAL PLL) and finds the RFC_CPROG that corresponds to the maximum transmitted power. The RFCAL is just a small part of a more complex algorithm fully described in the flowcharts in Section 9.4. The Power detection mode is a Normal mode in which the detector used for the calibrations is switched ON. This special mode enables power sensing at the input of the TDA18271HD and makes the power scan algorithm possible (see Section 9.4.8 "Flowchart TDA18271PowerScan").
9.3.9 Description of Easy prog byte 5
Table 19. EP5 - Easy prog byte 5 (subaddress 07h) bit description Legend: * power-on reset value. Bit 7 Symbol EXTENDED_REG Access Value R/W 1 0* Description enables extended register addressing extended register (10h to 26h) limited register (00h to 0Fh); only 1 byte can be programmed after address 0Fh within 1 transmission gain step for image rejection calibration must be set to logic 0 image rejection measurement frequency range (see Table 53)
6 to 4 IR_GSTEP[2:0] 3 2 to 0 IR_MEAS[2:0]
R/W R/W R/W
011* 0* 000*
9.3.10 Description of Cal post-divider byte
Table 20. CPD - Cal post-divider byte (subaddress 08h) bit description Legend: * power-on reset value. Bit 7 to 0 Symbol CAL_POST_DIV[7:0] Access R/W Value 00h* Description calibration synthesizer post-divider (see Table 48)
9.3.11 Description of Cal divider bytes 1, 2 and 3
CD1, CD2 and CD3 - Cal divider bytes 1, 2 and 3 (address 09h, 0Ah and 0Bh) bit description Legend: * power-on reset value. Address Register Bit 09h 0Ah 0Bh CD1 CD2 CD3 7 Symbol Access Value Description R/W R/W R/W 0* 00h* 00h* 00h* must be set to 0 calibration synthesizer main divider bits Table 21.
6 to 0 CAL_DIV[22:16] R/W 7 to 0 CAL_DIV[15:8] 7 to 0 CAL_DIV[7:0]
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9.3.12 Description of Main post-divider byte
Table 22. MPD - Main post-divider byte (subaddress 0Ch) bit description Legend: * power-on reset value. Bit 7 Symbol IF_NOTCH Access R/W Value 0* Description adds a DC notch in IF for better adjacent channels rejection; depends on standards; see Table 43 LO synthesizer post-divider; see Table 47
6 to 0
MAIN_POST_DIV[6:0]
R/W
000
9.3.13 Description of Main divider bytes 1, 2 and 3
Table 23. MD1, MD2 and MD3 - Main divider bytes 1, 2 and 3 (address 0Dh, 0Eh and 0Fh) bit description Legend: * power-on reset value. Address Register Bit 0Dh 0Eh 0Fh MD1 MD2 MD3 7 Symbol Access Value Description R/W R/W R/W 0* 00h* 00h* 00h* must be set to 0 LO synthesizer main divider bits
6 to 0 MAIN_DIV[22:16] R/W 7 to 0 MAIN_DIV[15:8] 7 to 0 MAIN_DIV[7:0]
9.3.14 Description of Extended bytes 1 to 23
Table 24. EB1 to EB23 - Extended bytes 1 to 23 (address 10h to 26h) bit description Legend: * power-on reset value. Address 10h Register EB1 Bit 7 to 3 2 Symbol EB1[7:3] CALVCO_FORLON Access R R 1* 0 1 AGC1_ALWAYS_ MASTERN R Value 1 1111* Description extended byte 1 determines VCO used during Normal mode operations LO VCO is used CAL VCO is used enables AGC1 normal operation whatever the tuner type (master or slave) 1* 0 0 AGC1_FIRSTN R 1* 0 11h 12h EB2 EB3 7 to 0 7 to 0 EB2[7:0] EB3[7:0] R/W R/W 0000 0001* 1000 0100* normal operation for the master; 6 dB fixed for the slave normal operation for both the master and the slave determines which AGC will be updated when detectors 1 and 2 are active AGC1 and AGC2 both updated AGC1 has priority on AGC2 extended byte 2 extended byte 3
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Table 24. EB1 to EB23 - Extended bytes 1 to 23 (address 10h to 26h) bit description ...continued Legend: * power-on reset value. Address 13h Register EB4 Bit 7 to 6 5 Symbol EB4[7:6] LO_FORCESRCE Access R/W R/W Value 01* 1 Description extended byte 4 forces the main PLL charge pump to source current to the main PLL loop filter no force extended byte 4 extended byte 5 extended byte 6 extended byte 7 forces the CAL PLL charge pump to source current to the CAL PLL loop filter no force extended byte 7 signal sensed by the power detector used during calibrations 1 0* 6 to 4 3 2 to 0 18h 19h 1Ah 1Bh EB9 EB10 EB11 EB12 7 to 0 5 to 0 7 to 0 5 EB8[6:4] EB8[3] EB8[2:0] EB9[7:0] CID_GAIN[5:0] EB11[7:0] PD_AGC1_DET R/W R R/W W R R R/W R R/W 1 0* 4 PD_AGC2_DET R/W 1 0* 3 to 0 1Ch EB13 7 6 to 4 1 to 0 1Dh 1Eh 1Fh EB14 EB15 EB16 7 to 0 7 to 4 3 to 0 7 to 0 EB12[3:0] EB13[7] RFC_K[2:0] EB13[1:0] RFC_CPROG[7:0] EB15[7:4] EB15[3:0] EB16[7:0] R/W R/W R/W R/W R/W R/W R/W R W 000X XX00* extended byte 16 0111* 1* 100* 00* 10* 0000 0000* 1000 XXXX* 0000 0000* 00* 1000 0110* 00* extended byte 9 extended byte 10 calibration power detector output extended byte 11 extended byte 12 AGC1 detector power-down no power-down AGC2 detector power-down no power-down extended byte 12 extended byte 13 parameters used during the RF tracking filter calibration (see Table 46) extended byte 13 tuning word of the RF tracking filters extended byte 15 111 0101* out of range in range extended byte 8
0* 4 to 0 14h 15h 16h EB5 EB6 EB7 7 to 0 7 to 0 5 EB4[4:0] EB5[7:0] EB6[7:0] R/W R/W R/W R/W 0 0001* 0000 0001* 1000 0100* 01* 1
7 and 6 EB7[7:6]
CAL_FORCESRCE R/W
0* 4 to 0 17h EB8 7 EB7[4:0] CID_ALARM R/W R 0 1000*
7 and 6 EB10[7:6]
7 and 6 EB12[7:6]
3 and 2 RFC_M[1:0]
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Table 24. EB1 to EB23 - Extended bytes 1 to 23 (address 10h to 26h) bit description ...continued Legend: * power-on reset value. Address 20h 21h Register EB17 EB18 Bit 7 to 0 7 Symbol EB17[7:0] AGC1_LOOP_OFF Access W R/W 1 0* 6 to 2 EB18[6:2] R/W R/W 00* 01 10 11 22h 23h EB19 EB20 7 to 0 5 EB19[7:0] FORCE_LOCK W W W 1 0* 4 to 0 24h EB21 7 EB20[4:0] AGC2_LOOP_OFF W R/W 1 0* 6 to 2 EB21[6:2] R/W R/W 00* 01 10 11 25h EB22 7 6 to 4 3 to 0 26h EB23 7 to 3 2 1 0 EB22[7] RF_TOP[2:0] IF_TOP[3:0] EB23[7:3] FORCELP_ FC2_EN LP_FC EB23[0] R R/W R/W R/W R/W R/W R/W 0* 100* 1000* 1 0110* 0* 0* 0* extended byte 23 00000* 1 and 0 AGC2_GAIN[1:0] X XXXX* 000X XX00* 10* 7 and 6 EB20[7:6] 00000* 1 and 0 AGC1_GAIN[1:0] Value 000X XXXX* Description extended byte 17 turns the AGC1 loop off on extended byte 18 AGC1 gain 6 dB 9 dB 12 dB 15 dB extended byte 19 extended byte 20 forces the internal lock indicator forced to logic 1 not forced extended byte 20 turns the AGC2 loop off on extended byte 21 AGC2 gain -15 dB -12 dB -9 dB -6 dB extended byte 22 Take-Over Point of the RF AGC, detection in RF Take-Over Point of the RF AGC, detection in IF extended byte 23 FM filter selection; see Table 25 and Table 26
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Low-pass cut-off frequency when using RF_IN input FORCELP_FC2_EN LP_FC 1 0 0 0 0 1 X X X X STD[1:0] XX 00 01 10 11 Cut-off frequency (MHz) 1.5 6 7 8 9
Table 25. RF input RF_IN
Table 26. RF input FM_IN
Low-pass cut-off frequency when using FM_IN input FORCELP_FC2_EN LP_FC 1 1 1 1 1 0 0 0 0 1 STD[1:0] 00 01 10 11 XX Cut-off frequency (MHz) 6 7 8 9 1.5
9.4 I2C-bus programming flowcharts
The following flowcharts describe how to:
* Initialize the TDA18271HD * Launch the calibrations * Go to Normal mode
The image rejection calibration and RF tracking filter calibration must be launched exactly as described in the flowchart, otherwise bad calibration or even blocking of the TDA18211HD can result making it impossible to communicate via the I2C-bus. Proper internal initialization requires switching to Normal mode using a single I2C-bus sequence from subaddresses 03h to 0Fh.
9.4.1 Flowchart explanation
This section provides instructions for reading the flowcharts.
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MS actions registers to update in the software internal table Internal table IR_GSTEP = 2h initialization phase I2C_XTOUT_ASYM = 1 PD_AGC1_DET = 1 IR_GSTEP = 2h, I2C_XTOUT_ASYM = 1, PD_AGC1_DET = 1 -
master or slave for I2C-bus write tuner registers update
I2C-bus EP5 EB12 EB13 -
EP5 EB12 EB13 EP1...CD2 EP1...EP2, MD3
001aag935
-
Fig 3.
Programming sequence
1. I2C-bus write: - IR_GSTEP is updated, no immediate I2C-bus write - I2C_XTOUT_ASYM is updated followed by an I2C-bus write of byte EP5 - PD_AGC1_DET is updated followed by an I2C-bus write of byte EB12 - I2C-bus write of byte EB13 with current value of the software internal register of byte EB13 I2C-bus read: - Subaddressing is not supported in read mode - The mandatory I2C-bus read access procedures to the TDA18271HD are described in Section 9.4.16 "Flowchart TDA18271Read" and Section 9.4.17 "Flowchart TDA18271ReadExtended" 2. Update at the same time is indicated by separation with commas: IR_GSTEP, I2C_XTOUT_ASYM and PD_AGC1_DET are updated, no I2C-bus registers updated 3. I2C-bus registers update bytes EP5, EB12 and EB13 4. Bytes EP1 to CD2 are written in a single I2C-bus sequence Example: Start C0 03 EP1 EP2 EP3 EP4 EP5 CPD CD1 CD2 Stop 5. Bytes EP1, EP2 and MD3 are written in as many I2C-bus sequences as needed Example: Start C0 03 EP1 EP2 Stop Start C0 0F MD3 Stop
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X X X X X X X X
stored or already calculated data
input variable
result of an operation
output variable
001aag722
Fig 4.
Blocks used in the flowcharts
I2C-bus initialization sequence Call TDA18271FixedContentsI2Cupdate MS_init Calibrate the RF tracking filters Call TDA18271CalcRFFilterCurve Back to POR Call TDA18271MSPOR
001aah042
Master/slave variable MS_init is input for each of the three procedures.
Fig 5.
Variable used in multiple procedures
xx_in XY_map
Find yy = f(xx) in XY_map
yy_out
001aag822
xx is a list of values stored in the first column of the map XY_map. yy is a list of values stored in column in XY_map yy_out is the particular value of yy to find row n. xx(n - 1) < xx_in xx(n)
a. General description to find a value in a table
650 MHz KM_map Find RFC_K = fRF(max) in KM_map
RFC_K
001aag723
Finding the row of RFC_K: 350000 < 650000 720000. Result n = 1. The value of RFC_K is then 3; see Table 46
b. Example to find the value RFC_K corresponding to fRF = 650 MHz in the KM_map Fig 6. Finding a value in a table
Units: In the flowcharts, hexadecimal values end with "h", decimal values with "d".
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9.4.2 Flowchart TDA18271SetRf_dual
The initialization phase has to be launched before any SetRf.
Table 27. Function Description Input Table Output
[1]
TDA18271SetRf_dual Description protocol top view for a dual tuner application RF_freq, Standard (from microcontroller), MS (from microcontroller)[1] Reference
MS = 1: master is selected for the channel configuration; MS = 0: slave is selected for the channel configuration.
Start TDA18271SetRf_dual
Yes
init_done = 1 No
Master and slave initialization Call TDA18271InitCal
TMVALUE_RFCAL init_done
TMVALUE_RFCAL
Set the RF tracking filters Call TDA18271RFTrackingFiltersCorrection
RF_freq MS Standard RF_freq MS Set the tuner to the wanted channel Call TDA18271ChannelConfiguration
End TDA18271SetRf_dual
001aah043
Fig 7.
Flowchart TDA18271SetRf_dual
9.4.3 Flowchart TDA18271InitCal
Table 28. Function Description Input Table Output TDA18271InitCal Description systematic initializations for master and slave tuners MS_init TMVALUE_RFCAL, init_done Reference
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Start TDA18271InitCal
MS_init = 1
MS_init
Master initialization I2C-bus initialization sequence Call TDA18271FixedContentsI2Cupdate MS_init Calibrate the RF tracking filters Call TDA18271CalcRFFilterCurve Back to POR Call TDA18271MSPOR
TMVALUE_RFCAL
MS_init = 0
MS_init
Slave initialization I2C-bus initialization sequence Call TDA18271FixedContentsI2Cupdate MS_init Calibrate the RF tracking filters Call TDA18271CalcRFFilterCurve Back to POR Call TDA18271MSPOR
init_done = true
init_done
End TDA18271InitCal
001aah044
Fig 8.
Flowchart TDA18271InitCal
9.4.4 Flowchart TDA18271FixedContentsI2Cupdate
Table 29. Function Description TDA18271FixedContentsI2Cupdate Description update and write the TDA18271HD registers sequential update of AGC1 and AGC2 image calibration algorithm Input Table Output MS Reference
The register contents are not described in detail as this procedure is not to be modified.
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Start TDA18271FixedContentsI2Cupdate
MS
Actions Internal table update with correct values
Internal table TM = 08h PL = 80h EP1 = C6h EP2 = DFh EP3 = 16h EP4 = 60h EP5 = 80h CPD = 80h CD1 = 00h CD2 = 00h CD3 = 00h MPD = 00h MD1 = 00h MD2 = 00h MD3 = 00h EB1 = FCh EB2 = 01h EB3 = 84h EB4 = 41h EB5 = 01h EB6 = 84h EB7 = 40h EB8 = 07h EB9 = 00h EB10 = 00h EB11 = 96h EB12 = 33h EB13 = C1h EB14 = 00h EB15 = 8Fh EB16 = 00h EB17 = 00h EB18 = 8Ch EB19 = 00h EB20 = 20h EB21 = B3h EB22 = 48h EB23 = B0h -
I2C-bus TM...EB23 IRCAL mid band initialization EP5 = 82h CPD = A8h CD2 = 00h MPD = A9h MD1 = 73h MD2 = 1Ah EP3...MD3 IRCAL low band initialization EP3 = 1Fh EP4 = 66h EP5 = 81h CPD = CCh CD1 = 6Ch CD2 = 00h CD3 = 00h MPD = CDh MD1 = 77h MD2 = 08h MD3 = 00h EB4 = 61h EP3...MD3 EB4 IRCAL high band initialization EP5 = 83h CPD = 98h CD1 = 65h CD2 = 00h MPD = 99h MD1 = 71h MD2 = CDh EP3...MD3
Tuner registers update Wait 5 ms - PLL locking Launch detector Wait 5 ms - measurement CAL PLL update
Tuner registers update MAIN PLL CP source on Wait 1 ms MAIN PLL CP source off Wait 5 ms - PLL locking
-
EP1
EB4 = 41h
EB4
EP5 = 87h CD1 = 65h CD2 = 50h -
EP3...CD3
Tuner registers update Launch detector Wait 5 ms - measurement Launch optimization algorithm CAL PLL update EP5 = 85h CPD = CBh CD1 = 66h CD2 = 70h EP3...CD3 Wait 30 ms - optimization Back to normal mode Synchronization EP1 Wait 5 ms - PLL locking
-
EP2
EP4 = 64h -
EP4 EP1
Tuner registers update Wait 5 ms - PLL locking Launch optimization algorithm Wait 30 ms - optimization
-
EP2
End TDA18271FixedContentsI2Cupdate
Tuner registers update
AGC1 gain setup
EB17 = 00h EB17 = 03h EB17 = 43h EB17 = 4Ch
EB17 EB17 EB17 EB17 Tuner registers update Wait 5 ms - PLL locking Launch detector Wait 5 ms - measurement CAL PLL update
-
EP1
EP5 = 86h CPD = A8h CD1 = 66h CD2 = A0h -
EP3...CD3
Tuner registers update Wait 5 ms - PLL locking Launch optimization algorithm Wait 30 ms - optimization
-
EP2
001aah045
Fig 9.
Flowchart TDA18271FixedContentsI2Cupdate
9.4.5 Flowchart TDA18271CalcRFFilterCurve
Table 30. Function Description Input Table Output TDA18271CalcRFFilterCurve Description calculate the RF filter curve coefficients RF1_default, RF2_default, RF3_default, MS RF_BAND_map TMVALUE_RFCAL Table 45 "RF_BAND_map" Reference
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Start TDA18271CalcRFFilterCurve
Wait 200 ms for die temperature stabilization
PowerScan Initialization Call TDA18271PowerScanInit
fRF(max) = 47900 kHz fRF(max) RF_Band 0 filters calibration Call TDA18271RFTrackingFiltersInit
fRF(max) RF1_0, RF_A1_0, RF_B1_0
fRF(max) = 61100 kHz fRF(max) RF_Band 1 filters calibration Call TDA18271RFTrackingFiltersInit
fRF(max) RF1_1, RF_A1_1, RF_B1_1
fRF(max) = 152600 kHz fRF(max) RF_Band 2 filters calibration Call TDA18271RFTrackingFiltersInit
fRF(max) RF1_2, RF_B1_2, RF2_2, RF_A1_2
fRF(max) = 164700 kHz MS fRF(max) RF_Band 3 filters calibration Call TDA18271RFTrackingFiltersInit
fRF(max) RF1_3, RF_A1_3, RF_B1_3
fRF(max) = 203500 kHz fRF(max) RF_Band 4 filters calibration Call TDA18271RFTrackingFiltersInit
fRF(max) RF1_4, RF_A1_4, RF_B1_4
fRF(max) = 457800 kHz fRF(max) RF_Band 5 filters calibration Call TDA18271RFTrackingFiltersInit
fRF(max) RF1_5, RF_B1_5, RF2_5, RF_A1_5, RF3_5, RF_A2_5, RF_B2_5
fRF(max) = 865000 kHz fRF(max) RF_Band 6 filters calibration Call TDA18271RFTrackingFiltersInit
fRF(max) RF1_6, RF_B1_6, RF2_6, RF_A1_6, RF3_6, RF_A2_6, RF_B2_6
Read die current temperature Call TDA18271ThermometerRead
TMVALUE_RFCAL
End TDA18271CalcRFFilterCurve
001aah046
Variable RF_max is used for frequency fRF(max).
Fig 10. Flowchart TDA18271CalcRFFilterCurve
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9.4.6 Flowchart TDA18271RFTrackingFiltersInit
Table 31. Function Description Input Table Output TDA18271RFTrackingFiltersInit Description calculate the RF filter curve coefficients used for their approximation fRF(max), MS RF_CAL_map (Cprog_table = f (frequency)) RF1, RF2, RF3, RF_A1, RF_B1, RF_A2, RF_B2 Table 51 "RF_CAL_map" Reference
bcal is a boolean output from TDA18271PowerScan: bcal = 1 (true): enables the calibration of the RF tracking filters bcal = 0 (false): no calibration is performed, default values for RFC_CPROG are used
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Start TDA18271RFTrackingFiltersInit RF_A1 = 0, RF_B1 = 0, RF_A2 = 0, RF_B2 = 0 RF1_default Find RF1_default, RF2_default, RF3_default = fRF(max) in RF_Band_map Look for optimized calibration frequency Call TDA18271PowerScan No RF1_default, RF2_default, RF3_default RF1 MS bcal RF1
MS Find Cprog_cal1 to track RF1 Call TDA18271CalibrateRF
bcal = 1 Yes
RF1
Cprog_cal1
RF1 RF_CAL_map
Find Cprog_table = fRF(max) in RF_CAL_map bcal = 0 Yes No
Cprog_table1
Cprog_table1 RF1 Cprog_cal1 Cprog_table1
Cprog_cal1 = Cprog_table1
Cprog_cal1
RF_B1 = Cprog_cal1 - Cprog_table1 Yes
RF_B1 RF_A1 End TDA18271 RFTrackingFiltersInit
RF2_default = 0 RF2_default No MS Look for optimized calibration frequency Call TDA18271PowerScan
bcal RF2 No
MS Find Cprog_cal2 to track RF2 Call TDA18271CalibrateRF
bcal = 1 Yes
RF2
RF2
Cprog_cal2
RF2 RF_CAL_map
Find Cprog_table = fRF(max) in RF_CAL_map No
Cprog_table2
bcal = 0 Yes Cprog_table2 RF1 RF2 Cprog_cal1 Cprog_cal2 Cprog_table1 Cprog_table2 RF3_default No MS Look for optimized calibration frequency Call TDA18271PowerScan Cprog_cal2 = Cprog_table2
Cprog_cal2
RF_A1 = (Cprog_cal2 - Cprog_table2 - Cprog_cal1 + Cprog_table1) / (RF2 - RF1)
RF_A1
RF3_default = 0
Yes
End TDA18271 RFTrackingFiltersInit
bcal RF3 No RF3
MS Find Cprog_cal3 to track RF3 Call TDA18271CalibrateRF
bcal = 1 Yes
RF3
Cprog_cal3
RF3 RF_CAL_map
Find Cprog_table = fRF(max) in RF_CAL_map No
Cprog_table3
bcal = 0 Yes Cprog_table3 Cprog_cal3 = Cprog_table3
Cprog_cal3
RF2 RF3 Cprog_cal2 Cprog_cal3 Cprog_table2 Cprog_table3
RF_A2 = (Cprog_cal3 - Cprog_table3 - Cprog_cal2 + Cprog_table2)/(RF3 - RF2) RF_B2 = Cprog_cal2 - Cprog_table2 End TDA18271RFTrackingFiltersInit
RF_A2 RF_B2
001aah047
Fig 11. Flowchart TDA18271RFTrackingFiltersInit
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9.4.7 Flowchart TDA18271PowerScanInit
Table 32. Function Description Input Table Output TDA18271PowerScanInit Description fixed settings of the TDA18271PowerScan MS Reference
Frequency unit during the algorithm in kHz. Variable count homogeneous to kHz.
Start TDA18271PowerScanInit
MS
Actions Set standard mode to digital mode
Internal table STD = 12, IF_LEVEL = 0 CAL_MODE = 0 AGC1_GAIN = 0 AGC2_GAIN = 0 FORCELP_FC2_EN = 1, LP_FC = 1 -
I2C-bus -
Tuner registers update Set AGC1_GAIN to 6 dB Set AGC2_GAIN to -15 dB 1.5 MHz low-pass filter
EP3...EP4 EB18 -
Tuner register update
EB21...EB23
End TDA18271PowerScanInit
001aah048
Fig 12. Flowchart TDA18271PowerScanInit
9.4.8 Flowchart TDA18271PowerScan
Table 33. Function Description Input Table TDA18271PowerScan Description find an interference-free calibration frequency freq_input, MS RF_BAND_map, RF_CAL_map, CID_Target_map Table 45 "RF_BAND_map" Table 51 "RF_CAL_map" Table 54 "CID_Target_map" Output bcal, freq_output Reference
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Silicon Tuner IC
Start TDA18271PowerScan RF_BAND_map RF_CAL_map CID_Target_map MS Actions Find RF_BAND = fRF(max) in RF_BAND_map (MS) Find Cprog_table = fRF(max) in RF_CAL_map Find GAIN_TAPER = fRF(max) in GAIN_TAPER_map Find CID_Target count_limit = fRF(max) in CID_Target_map Tuner register update freq_MAINPLL = freq_input = 1 MHz Downconvert freq_input to 1 MHz Call TDA18271CalcMAINPLL Wait 5 ms - PLL locking Detection mode Launch power detection measurement Read power detection information Call TDA18271ReadExtended Algorithm Initialization sgn = 1 freq_output = freq_input bcal = 0 count = 0 wait = false CAL_MODE = 1 EP4 EP2 Internal table RF_BAND = RF_BAND RFC_Cprog = Cprog_table GAIN_TAPER = GAIN_TAPER CID_Target = CID_Target count_limit = count_limit I2C-bus -
MS
CID_Target count_limit EP2, EB14 freq_MAINPLL
freq_input
freq_MAINPLL
CID_GAIN
freq_input
sgn freq_output bcal count wait
No
CID_GAIN < CID_Target
Yes sgn count freq_input freq_MAINPLL freq_MAINPLL = freq_input + (sgn x count) + 1 MHz Downconvert updated freq_input to 1 MHz Call TDA18271CalcMAINPLL No Wait 100 s - PLL locking Yes Wait 5 ms - PLL locking wait = false wait freq_MAINPLL
wait = true
Launch power detection measurement Read power detection information Call TDA18271ReadExtended count count = count + 200
-
EP2 CID_GAIN count
No
count > count_limit
Yes No sgn > 0 Yes sgn = - sgn count = 200 wait = true sgn count wait
CID_GAIN CID_Target
No
Yes freq_MAINPLL bcal = 1 freq_output = freq_MAINPLL - 1 MHz End TDA18271PowerScan bcal freq_output freq_input bcal = 0 freq_output = freq_input bcal freq_output
End TDA18271PowerScan
001aah049
Fig 13. Flowchart TDA18271PowerScan
TDA18271HD_4
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TDA18271HD
Silicon Tuner IC
9.4.9 Flowchart TDA18271CalibrateRF
Table 34. Function Description Input Table TDA18271RFCalibrateRF Description finds the Cprog for which freq_input is the central frequency of the RF tracking filters freq_input, MS BP_FILTER_map, KM_map and GAIN_TAPER_map Table 44 "BP_FILTER_map" Table 46 "KM_map" Table 49 "GAIN_TAPER_map" Output RFC_CPROG Reference
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Silicon Tuner IC
Start TDA18271CalibrateRF
MS
Actions Normal mode Switch OFF AGC1 Set AGC1_GAIN to 15 dB
Internal table CAL_MODE = 0 SM_LT = 1 AGC1_GAIN = 3h
I2C-bus EP4 EB18
BP_FILTER_map KM_map GAIN_TAPER_map freq_input MS
Frequency dependent parameters update Find BP_FILTER = fRF(max) in BP_FILTER_map Find GAIN_TAPER = fRF(max) in GAIN_TAPER_map Find RF_BAND = fRF(max) in RF_BAND_map (MS) Find RFC_K, RFC_M = fRF(max) in KM_map Tuner registers update MAIN PLL charge pump source CAL PLL charge pump source Force DC-DC converter to 0 V Disable PLLs lock RF tracking filters calibration mode Tuner registers update
BP_FILTER = BP_FILTER GAIN_TAPER = GAIN_TAPER RF_BAND = RF_BAND RFC_K = RFC_K, RFC_M = RFC_M LO_FORCESRCE = 1 CAL_FORCESRCE = 1 RFC_CPROG = 0 FORCE_LOCK = 0 CAL_MODE = 3h -
EP1 ... EP3, EB13 EB4 EB7 EB14 EB20 EP4 ... EP5
freq_input freq_input + 1 MHz
Set the internal calibration signal Call TDA18271CalcCALPLL Downconvert the calibration signal to 1 MHz Call TDA18271CalcMAINPLL Wait 5 ms Internal synchronization EP2, EP1, EP2, EP1
Normal operation for the MAIN PLL charge pump Normal operation for the CAL PLL charge pump Wait 10 ms - PLLs locking
LO_FORCESRCE = 0 CAL_FORCESRCE = 0
EB4 EB7
Launch the RF Tracking filters calibration Wait 60 ms - calibration ongoing Normal mode Switch ON AGC1 Set AGC1_GAIN to 6 dB Tuner registers update Synchronization
FORCE_LOCK = 1
EB20
CAL_MODE = 0 SM_LT = 0 AGC1_GAIN = 0 -
EB18 EP3 ... EP4 EP1
Get the calibration result Call TDA18271ReadExtended
RFC_CPROG
End TDA18271CalibrateRF
001aah050
Fig 14. Flowchart TDA18271CalibrateRF
TDA18271HD_4
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TDA18271HD
Silicon Tuner IC
9.4.10 Flowchart TDA18271MSPOR
Table 35. Function Description Input Table Output TDA18271MSPOR Description master or slave tuner goes to Power-On Reset (POR) mode MS Reference
Start TDA18271MSPOR
MS
Actions Power Up Detector 1 Turn AGC1 loop ON Set AGC1_GAIN to 6 dB Set AGC2_GAIN to -6 dB POR mode 1.5 MHz low-pass filter disabled
Internal table PD_AGC1_DET = 0 AGC1_LOOP_OFF = 0 AGC1_GAIN = 0 AGC2_GAIN = 3h SM = 1, SM_LT = 0, SM_XT = 0 FORCELP_FC2_EN = 0, LP_FC = 0
I2C-bus EB12 EB18 EP3 EB21 ... EB23
End TDA18271MSPOR
001aah051
Fig 15. Flowchart TDA18271MSPOR
9.4.11 Flowchart TDA18271RFTrackingFiltersCorrection
Table 36. Function TDA18271RFTrackingFiltersCorrection Description Reference
Description find the Cprog corresponding to the programmed central frequency freq_input Input Table freq_input, TMVALUE_RFCAL, MS RF_BAND_map, RF_CAL_DC_OVER_DT_map, RF_CAL_map Table 45 "RF_BAND_map" Table 50 "RF_CAL_DC_OVER_DT_map" Table 51 "RF_CAL_map"
Output
TDA18271HD_4
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Silicon Tuner IC
Start TDA18271RFTrackingFiltersCorrection
MS
Action Power-up TDA18271
Internal table
I2C-bus
SM = 0, SM_LT = 0, EP3 SM_XT = 0
Read current die temperature Call TDA18271ThermometerRead
TMVALUE_CURRENT
RF_CAL_map RF_BAND_map
Frequency dependent parameters update Find RFC_CPROG = fRF(max) in RF_CAL_map, Cprog_table = RFC_Cprog Find RF1, RF2, RF3, RF_A1, RF_A2, RF_B1, RF_B2 = fRF(max) in RF_BAND_map (MS)
freq_input MS No RF3 = 0 or freq_input < RF2 Yes
Cprog_table RF1 RF2 RF3 RF_A1 RF_A2 RF_B1 RF_B2
RF_A2 RF2 RF_B2 Cprog_table
Capprox = RF_A2 x (freq_input - RF2) + RF_B2 + Cprog_table
Capprox
RF_A1 RF1 RF_B1 Cprog_table
Capprox = RF_A1 x (freq_input - RF1) + RF_B1 + Cprog_table
Capprox
freq_input
freq_input
Capprox < 0
No
Capprox > 255
No
Yes Capprox = 0
Yes Capprox = 255
RF_CAL_DC_OVER_DT_map
Find dCoverdT = fRF(max) in RF_CAL_DC_OVER_DT_map
dCoverdT
freq_input
dCoverdT TMVALUE_CURRENT
Calculate temperature compensation RFCAL_TCOMP = dCoverdT x (TMVALUE_CURRENT - TMVALUE_RFCAL) / 1000
RFCAL_TCOMP
TMVALUE_RFCAL
Capprox RFCAL_TCOMP
Calculate final Cprog Cprog = Capprox + RFCAL_TCOMP
RFC_Cprog = Cprog
EB14
End TDA18271RFTrackingFiltersCorrection
001aah052
Fig 16. Flowchart TDA18271RFtrackingFiltersCorrection
TDA18271HD_4
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TDA18271HD
Silicon Tuner IC
9.4.12 Flowchart TDA18271ChannelConfiguration
Table 37. Function TDA18271ChannelConfiguration Description Reference
Description tunes the tuner according to the channel and broadcast configuration Input Table freq_input, MS, Standard STANDARD_DESCRIPTION_map, Table 43 "STANDARD_DESCRIPTION_map" BP_FILTER_map, RF_BAND_map, Table 44 "BP_FILTER_map" CAL_PLL_map, Table 45 "RF_BAND_map" GAIN_TAPER_map, IR_MEAS_map Table 48 "CAL_PLL_map" Table 49 "GAIN_TAPER_map" Table 53 "IR_MEAS_map" Output -
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Product data sheet Rev. 04 -- 19 May 2009
(c) NXP B.V. 2009. All rights reserved. TDA18271HD_4
NXP Semiconductors
Start TDA18271ChannelConfiguration
MS
Actions Standard Standard mode update Update TV broadcast parameters Switch RFAGC to high speed mode Normal mode Update IF output level Update IF notch frequency Update extended byte 22 Update IF center frequency Update FM_RFn
Internal table STD = STD from STANDARD_DESCRIPTION_map according to Standard value STD[2] = 0 CAL_MODE = 0 IF_LEVEL = IF_LEVEL IF_NOTCH = IF_NOTCH from STANDARD_DESCRIPTION_map according to Standard EB22 = EB22 IF_FREQ = IF_FREQ FM_RFn = FM_RFn
I2C-bus EB22 -
IF_freq
STANDARD_DESCRIPTION_ map
IR_MEAS_map BP_FILTER_map RF_BAND_map GAIN_TAPER_map freq_input MS
Disable power level indicator Update frequency dependent parameters Find IR_MEAS = fRF(max) in IR_MEAS_map Find BP_FILTER = fRF(max) in BP_FILTER_map Find RF_BAND = fRF(max) in RF_BAND_map (MS) Find GAIN_TAPER = fRF(max) in GAIN_TAPER_map
DIS_POWER_LEVEL = 1 IR_MEAS = IR_MEAS BP_FILTER = BP_FILTER RF_BAND = RF_BAND GAIN_TAPER = GAIN_TAPER
-
MS
Dual Tuner and AGC1 extra configurations managing MAIN VCO when Master, CAL VCO when Slave AGC1 always active AGC1 has priority on AGC2 Tuner registers update
CALVCO_FORLON = MS AGC1_ALWAYS_MASTERN = 0 AGC1_FIRSTN = 0 -
-
EB1
freq_input
freq_pll = freq_input + IF_freq
IF_freq Yes MS = 1 No
freq_pll freq_pll Tune to wanted channel frequency Call TDA18271CalcMAINPLL Tuner registers update MAIN PLL charge pump source Wait 1 ms Normal operation for the MAIN PLL Wait 20 ms Switch RFAGC to normal speed mode STD[2] = not (FM_RFn) EP3 LO_FORCESRCE = 0 EB4 LO_FORCESRCE = 1 CAL_PLL_map freq_pll TM ... EP5 EB4
Tune to wanted channel frequency Call TDA18271CalcMAINPLL Find CAL_POST_DIV = fLO(max) in CAL_PLL_map Tuner registers update CAL PLL charge pump source Wait 1 ms Normal operation for the CAL PLL Wait 20 ms Switch RFAGC to normal speed mode STD[2] = not (FM_RFn) EP3 CAL_FORCESRCE = 0 EB7 MPD = CAL_POST_DIV & 7Fh CAL_FORCESRCE = 1 MPD TM ... EP5 EB7
TDA18271HD
Silicon Tuner IC
End TDA18271ChannelConfiguration
End TDA18271ChannelConfiguration
001aah053
Fig 17. Flowchart TDA18271ChannelConfiguration
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Silicon Tuner IC
9.4.13 Flowchart TDA18271CalcMAINPLL
MPD, MD1, MD2 and MD3 are 8-bit registers. Arithmetical and logical operations performed on these registers are handled as binary operations. Dividing is right shifting and multiplying is left shifting.
Table 38. Function Description Input Table Output TDA18271CalcMAINPLL Description finds the correct values for the bytes MPD, MD1, MD2, MD3 and update the tuner registers freq_input, MS MAIN_PLL_map Table 47 "MAIN_PLL_map" Reference
Start TDA18271CalcMAINPLL MAIN_PLL_map Find MAIN_POST_DIV, Div = fLO(max) in MAIN_PLL_map freq_input MS MAIN_POST_DIV Div
Internal table MAIN_POST_DIV Update MPD byte MPD = MAIN_POST_DIV & 7Fh
I2C-bus -
Div MAIN_DIV = (Div x freq_input x 27) / 125 freq_input Update MD1, MD2, MD3 bytes MAIN_DIV Tuner registers update MD1 = (MAIN_DIV / 216) & 7Fh MD2 = (MAIN_DIV / 28) MD3 = MAIN_DIV MAIN_DIV
MPD ... MD3
End TDA18271CalcMAINPLL
001aah054
Fig 18. Flowchart TDA18271CalcMAINPLL
9.4.14 Flowchart TDA18271CalcCALPLL
CPD, CD1, CD2 and CD3 are 8-bit registers. Arithmetical and logical operations performed on these registers are handled as binary operations. Dividing is right shifting and multiplying is left shifting.
TDA18271HD_4
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Product data sheet
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TDA18271HD
Silicon Tuner IC
TDA18271CalcCALPLL Description finds the correct values for the bytes CPD, CD1, CD2, CD3 and update the tuner registers freq_input, MS CAL_PLL_map Table 48 "CAL_PLL_map" Reference
Table 39. Function Description Input Table Output
Start TDA18271CalcCALPLL CAL_PLL_map Find CAL_POST_DIV, Div = fLO(max) in CAL_PLL_map freq_input MS CAL_POST_DIV Div
Internal table CAL_POST_DIV Update CPD byte CPD = CAL_POST_DIV
I2C-bus -
Div CAL_DIV = (Div x freq_input x 27) / 125 freq_input Update CD1, CD2, CD3 bytes CAL_DIV Tuner registers update CD1 = (CAL_DIV / 216) & 7Fh CD2 = (CAL_DIV / 28) CD3 = CAL_DIV CAL_DIV
CPD ... CD3
End TDA18271CalcCALPLL
001aah055
Fig 19. Flowchart TDA18271CalcCALPLL
9.4.15 Flowchart TDA18271ThermometerRead
Table 40. Function TDA18271ThermometerRead Description Reference
Description turns the on-chip temperature sensor ON, reads the current temperature on the die and then turns the temperature sensor OFF Input Table Output MS THERMOMETER_map TMVALUE (temperature in C) Table 52 "THERMOMETER_map"
TDA18271HD_4
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Product data sheet
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Silicon Tuner IC
Start TDA18271ThermometerRead
MS
Actions Switch thermometer ON
Internal table TM_ON = 1
I2C-bus TM
Read thermometer information Call TDA18271Read
TM_RANGE TM_D
No
(TM_D = 0) and (TM_RANGE = 1) or (TM_D = 8) and (TM_RANGE = 0)
Yes Switch TM_RANGE Wait 10 ms - temperature sensing TM_RANGE = not (TM_RANGE) TM
Read thermometer information Call TDA18271Read
TM_RANGE TM_D
TM_D TM_RANGE
Find TMVALUE = f (TM_D, TM_RANGE) in THERMOMETER_map
TMVALUE
Switch thermometer OFF Normal mode
TM_ON = 0 CAL_MODE = 0
TM EP4
End TDA18271ThermometerRead
001aah056
Fig 20. Flowchart TDA18271ThermometerRead
9.4.16 Flowchart TDA18271Read
Table 41. Function Description Input Table Output TDA18271Read Description reads the first 16 bytes of the TDA18271HD MS an image of the tuner registers from TM to MD3 Reference
The internal software registers are never updated at any time during the read procedure but are updated when the TDA18271Read is called. The I2C-bus read in the TDA18271HD does not support subaddressing or variable length sequences. The chip can only be read by performing read sequences TDA18271Read (16 bytes) or TDA18271ReadExtended (39 bytes).
TDA18271HD_4
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Product data sheet
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Silicon Tuner IC
Start TDA18271Read
MS
Choose Read address = f (MS)
AddRead (1)
AddRead
Read the first 16 bytes starting at address Cx00h(2)
TM ...MD3
End TDA18271Read
001aah057
(1) AddRead = C1h, C3h, C5h or C7h. (2) x = 1, 3, 5 or 7.
Fig 21. Flowchart TDA18271Read
9.4.17 Flowchart TDA18271ReadExtended
Table 42. Function Description Input Table Output TDA18271ReadExtended Description read the first 39 bytes of the TDA18271HD MS an image of the tuner registers from TM to EB23 Reference
The internal software registers are not updated throughout a read procedure. The update is performed at the level of the call TDA18271ReadExtended.
Start TDA18271ReadExtended
MS
Choose Read address = f (MS)
AddRead (1)
AddRead
Read the first 39 bytes starting at address Cx00h(2)
TM ...EB23
End TDA18271ReadExtended
001aah058
(1) AddRead = C1h, C3h, C5h or C7h. (2) x = 1, 3, 5 or 7.
Fig 22. Flowchart TDA18271ReadExtended
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TDA18271HD
Silicon Tuner IC
9.5 Maps
Table 43. Standard Radio FM radio Analog TV Analog TV std B Analog TV std D/K Analog TV std G/H Analog TV std I Analog TV std L Analog TV std L' Analog TV std M/N Digital TV[3] ATSC 6 MHz DVB-T 6 MHz DVB-T 7 MHz DVB-T 8 MHz QAM 6 MHz QAM 8 MHz
[1] [2]
STANDARD_DESCRIPTION_map Selection STD[2:0] 000 101 110 FM_RFN 1 0 Recommended values[1] IF_LEVEL[2:0] IF_NOTCH 000 000 0 0 EB22[7:0][2] 2Ch 2Ch fIF (MHz) 1.25 6 6.9 7.1 7.25 6.9 1.25 100 100 0 001 1 37h 5.4 3.25 3.30 3.50 101 111 4 4 5
Recommended values for analog and digital reception with a TDA8295 IF demodulator and a TDA10048HN channel decoder respectively. EB22[7:0] is the byte of the Take-Over Points of the RF_AGC (bits RF_TOP[2:0] and bits IF_TOP[3:0]). The RF performances (see Section 13 "Characteristics") relate to these standard dependent arrangements. Any other combination of RF_TOP and IF_TOP fields is not recommended. Digital standard settings may vary, depending on channel decoder used.
[3]
Table 44. 62000 84000 100000 140000 170000 180000 865000
BP_FILTER_map BP_FILTER[2:0] 000 001 010 011 100 101 110
fRF(max) (kHz)
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Silicon Tuner IC
Table 45. fRF(max) (kHz) 47900 61100 152600 164700 203500 457800 865000
RF_BAND_map RF_BAND Used in flowchart [2:0] RF_A1 RF_B1 000 001 010 011 100 101 110 RF_A2 RF_B2 RF1 RF2 RF3 0 0 0 0 RF1_ default (kHz) 46000 52200 70100 156700 186250 RF2_ default (kHz) 0 0 136800 0 0 345000 697500 RF3_ default (kHz) 0 0 0 0 0 426000 842000
RF_A1_0 RF_B1_0 RF_A2_0 RF_B2_0 RF1_0 0 RF_A1_1 RF_B1_1 RF_A2_1 RF_B2_1 RF1_1 0 RF_A1_3 RF_B1_3 RF_A2_3 RF_B2_3 RF1_3 0 RF_A1_4 RF_B1_4 RF_A2_4 RF_B2_4 RF1_4 0
RF_A1_2 RF_B1_2 RF_A2_2 RF_B2_2 RF1_2 RF2_2 0
RF_A1_5 RF_B1_5 RF_A2_5 RF_B2_5 RF1_5 RF2_5 RF3_5 230000 RF_A1_6 RF_B1_6 RF_A2_6 RF_B2_6 RF1_6 RF2_6 RF3_6 489500 Table 46. 47900 61100 350000 720000 865000 KM_map RFC_K[2:0] 011 100 011 010 011 RFC_M[1:0] 10 01 00 01 11
fRF(max) (kHz)
The KM_map refers to parameters used during the RF tracking filter calibration. These parameters are frequency dependent.
Table 47. 33125 35500 38188 41375 45125 49688 55188 62125 66250 71000 76375 82750 90250 99375 110375 124250 132500 142000 152750 165500
TDA18271HD_4
MAIN_PLL_map MAIN_POST_DIV[6:0] 57h 56h 55h 54h 53h 52h 51h 50h 47h 46h 45h 44h 43h 42h 41h 40h 37h 36h 35h 34h Div[1] F0h E0h D0h C0h B0h A0h 90h 80h 78h 70h 68h 60h 58h 50h 48h 40h 3Ch 38h 34h 30h
(c) NXP B.V. 2009. All rights reserved.
fLO(max) (kHz)
Product data sheet
Rev. 04 -- 19 May 2009
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Silicon Tuner IC
MAIN_PLL_map ...continued MAIN_POST_DIV[6:0] 33h 32h 31h 30h 27h 26h 25h 24h 23h 22h 21h 20h 17h 16h 15h 14h 13h 12h 11h 10h Div[1] 2Ch 28h 24h 20h 1Eh 1Ch 1Ah 18h 16h 14h 12h 10h 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h
Table 47. 180500 198750 220750 248500 265000 284000 305500 331000 361000 397500 441500 497000 530000 568000 611000 662000 722000 795000 883000 994000
[1]
fLO(max) (kHz)
Used in Section 9.4.13 "Flowchart TDA18271CalcMAINPLL".
Table 48. 33813 36625 39938 43938 48813 54938 62813 67625 73250 79875 87875 97625 109875 125625 135250 146500 159750
TDA18271HD_4
CAL_PLL_map CAL_POST_DIV[7:0] DDh DCh DBh DAh D9h D8h D3h CDh CCh CBh CAh C9h C8h C3h BDh BCh BBh
Rev. 04 -- 19 May 2009
fLO(max) (kHz)
Div[1] D0h C0h B0h A0h 90h 80h 70h 68h 60h 58h 50h 48h 40h 38h 34h 30h 2Ch
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Silicon Tuner IC
CAL_PLL_map ...continued CAL_POST_DIV[7:0] BAh B9h B8h B3h ADh ACh ABh AAh A9h A8h A3h 9Dh 9Ch 9Bh 9Ah 99h 98h Div[1] 28h 24h 20h 1Ch 1Ah 18h 16h 14h 12h 10h 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h
Table 48. 175750 195250 219750 251250 270500 293000 319500 351500 390500 439500 502500 541000 586000 639000 703000 781000 879000
[1]
fLO(max) (kHz)
Used in Section 9.4.14 "Flowchart TDA18271CalcCALPLL".
Table 49.
GAIN_TAPER_map fRF(max) (kHz) 1 2 154300 156100 157800 159500 161200 163000 164700 170200 175800 181300 186900 192400 198000 203500 3 216200 228900 241600 254400 267100 279800 292500 305200 4 476300 494800 513300 531800 550300 568900 587400 605900 624400 642900 661400 679900 698400
(c) NXP B.V. 2009. All rights reserved.
GAIN_TAPER[4:0][1] 1Fh 1Eh 1Dh 1Ch 1Bh 1Ah 19h 18h 17h 16h 15h 14h 13h 12h 11h 10h 0Fh 0Eh 0Dh
TDA18271HD_4
45400 45800 46200 46700 47100 47500 47900 49600 51200 52900 54500 56200 57800 59500 61100 67600
Product data sheet
Rev. 04 -- 19 May 2009
46 of 70
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TDA18271HD
Silicon Tuner IC
GAIN_TAPER_map ...continued fRF(max) (kHz) 1 2 3 317900 330700 343400 356100 368800 381500 394200 406900 419700 432400 445100 457800 4 716900 735400 753900 772500 791000 809500 828000 846500 865000 74200 80700 87200 93800 100300 106900 113400 119900 126500 133000 139500 146100 152600
Table 49.
GAIN_TAPER[4:0][1] 0Ch 0Bh 0Ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h
[1]
The gain taper function compensates for any systematic RF gain ripple, giving a flat RF gain with frequency.
Table 50. 47900 55000 61100 64000 82000 84000 119000 124000 129000 134000 139000 144000 149000 152600 154000 164700 203500 353000 356000 359000 363000 366000 369000
TDA18271HD_4
RF_CAL_DC_OVER_DT_map fRF(max) (kHz) dCoverdT[1] 383000 386000 389000 393000 396000 399000 402000 404000 407000 409000 412000 414000 417000 419000 422000 424000 427000 429000 432000 434000 437000 439000 442000 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h fRF(max) (kHz) dCoverdT[1] 457800 465000 477000 483000 502000 508000 519000 522000 524000 534000 549000 554000 584000 589000 658000 664000 669000 699000 704000 709000 714000 724000 729000
Rev. 04 -- 19 May 2009
fRF(max) (kHz) dCoverdT[1] 0h 0h 0Ah 0Ah 14h 19h 1Ch 20h 2Ah 32h 39h 3Eh 3Fh 40h 40h 41h 32h 19h 1Ah 1Bh 1Ch 1Dh 1Eh
fRF(max) (kHz) dCoverdT[1] 754000 759000 764000 769000 774000 779000 784000 789000 794000 799000 804000 809000 814000 819000 824000 829000 834000 839000 844000 849000 854000 859000 865000 3Ch 3Dh 3Eh 3Fh 40h 41h 43h 46h 48h 4Bh 4Fh 54h 59h 5Dh 61h 68h 6Eh 75h 7Eh 82h 84h 8Fh 9Ah
(c) NXP B.V. 2009. All rights reserved.
3Ch 0Fh 12h 14h 19h 1Bh 1Ch 1Dh 1Eh 1Fh 20h 22h 24h 26h 27h 2Ch 2Dh 2Eh 30h 31h 32h 33h 36h
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Table 50. 373000 376000 379000
[1]
RF_CAL_DC_OVER_DT_map ...continued fRF(max) (kHz) dCoverdT[1] 444000 447000 449000 39h 3Ah 3Bh fRF(max) (kHz) dCoverdT[1] 739000 744000 749000 38h 39h 3Bh fRF(max) (kHz) dCoverdT[1] 1Fh 20h 21h
fRF(max) (kHz) dCoverdT[1]
Used in flowcharts.
Table 51. fRF(max) (kHz) 41000 43000 45000 46000 47000 47900 49100 50000 51000 53000 55000 56000 57000 58000 59000 60000 61100 63000 64000 65000 66000 67000 68000 70000 71000 72000 73000 74000 75000 76000 77000 78000 80000
TDA18271HD_4
RF_CAL_map Cprog_ table 0Fh 1Ch 2Fh 39h 40h 50h 16h 18h 20h 28h 2Bh 32h 35h 3Eh 43h 4Eh 55h 0Fh 11h 12h 15h 16h 17h 19h 1Ch 1Dh 1Fh 20h 21h 24h 25h 27h 28h fRF(max) (kHz) 127000 128000 129000 130000 131000 132000 133000 134000 135000 136000 137000 138000 139000 140000 141000 142000 143000 144000 145000 146000 147000 148000 149000 150000 151000 152000 152600 154000 155000 156000 157000 158000 159000 Cprog_ table 6Eh 70h 71h 75h 77h 78h 7Bh 7Eh 81h 82h 87h 88h 8Dh 8Eh 91h 95h 9Ah 9Dh A1h A2h A4h A9h AEh B0h B1h B7h BDh 20h 22h 24h 25h 27h 29h fRF(max) (kHz) 208000 212000 216000 217000 218000 220000 222000 225000 228000 231000 234000 235000 236000 237000 240000 242000 244000 247000 249000 252000 253000 254000 256000 259000 262000 264000 267000 269000 271000 273000 275000 277000 279000 Cprog_ table 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh fRF(max) (kHz) 370000 372000 375000 376000 377000 379000 382000 384000 385000 386000 388000 390000 393000 394000 396000 397000 398000 400000 402000 403000 407000 408000 409000 410000 411000 412000 413000 414000 417000 418000 420000 422000 423000 Cprog_ table 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h fRF(max) (kHz) 521000 525000 529000 533000 539000 541000 547000 549000 551000 556000 561000 563000 565000 569000 571000 577000 580000 582000 584000 588000 591000 596000 598000 603000 604000 606000 612000 615000 617000 621000 622000 625000 632000 Cprog_ table 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h fRF(max) (kHz) 740000 741000 742000 743000 745000 747000 748000 750000 752000 754000 757000 758000 760000 763000 764000 766000 767000 768000 773000 774000 776000 777000 778000 779000 781000 783000 784000 785000 786000 793000 794000 795000 797000 Cprog_ table 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h
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Silicon Tuner IC
Table 51. fRF(max) (kHz) 81000 82000 83000 84000 85000 86000 87000 88000 89000 90000 91000 93000 94000 95000 96000 97000 99000 100000 102000 103000 105000 106000 107000 108000 110000 111000 112000 113000 114000 115000 116000 117000 119000 120000 121000 122000 123000 124000 125000 126000
TDA18271HD_4
RF_CAL_map ...continued Cprog_ table 29h 2Dh 2Eh 2Fh 31h 33h 34h 35h 37h 38h 39h 3Ch 3Eh 3Fh 40h 42h 45h 46h 48h 4Ah 4Dh 4Eh 50h 51h 54h 56h 57h 58h 59h 5Ch 5Dh 5Fh 60h 64h 65h 66h 68h 69h 6Ch 6Dh fRF(max) (kHz) 160000 161000 163000 164000 164700 166000 167000 168000 169000 170000 172000 173000 174000 175000 176000 178000 179000 180000 181000 182000 183000 184000 185000 186000 187000 188000 189000 190000 191000 192000 193000 194000 195000 196000 198000 200000 201000 202000 203500 206000 Cprog_ table 2Ch 2Dh 2Eh 2Fh 30h 11h 12h 13h 14h 15h 16h 17h 18h 1Ah 1Bh 1Dh 1Eh 1Fh 20h 21h 22h 24h 25h 26h 27h 29h 2Ah 2Ch 2Dh 2Eh 2Fh 30h 33h 35h 36h 38h 3Ch 3Dh 3Eh 0Eh fRF(max) (kHz) 282000 284000 286000 287000 290000 293000 295000 297000 300000 303000 305000 306000 307000 310000 312000 315000 318000 320000 323000 324000 325000 327000 331000 334000 337000 339000 340000 341000 343000 345000 349000 352000 353000 355000 357000 359000 361000 362000 364000 368000 Cprog_ table 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h fRF(max) (kHz) 424000 427000 428000 429000 432000 434000 435000 436000 437000 438000 439000 440000 441000 442000 445000 446000 447000 448000 449000 450000 452000 453000 454000 456000 457800 461000 468000 472000 473000 474000 481000 486000 491000 498000 499000 501000 506000 511000 516000 520000 Cprog_ table 79h 7Ah 7Bh 7Dh 7Fh 80h 81h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Eh 8Fh 90h 91h 93h 94h 96h 98h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh fRF(max) (kHz) 633000 634000 642000 643000 647000 650000 652000 657000 661000 662000 665000 667000 670000 673000 676000 677000 681000 683000 686000 688000 689000 691000 695000 698000 703000 704000 705000 707000 710000 712000 717000 718000 721000 722000 723000 725000 727000 730000 732000 735000 Cprog_ table 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h fRF(max) (kHz) 799000 801000 802000 803000 804000 810000 811000 812000 814000 816000 817000 818000 820000 821000 822000 828000 829000 830000 831000 833000 835000 836000 837000 838000 840000 842000 845000 846000 847000 848000 852000 853000 858000 860000 861000 862000 863000 864000 865000 Cprog_ table 8Ah 8Bh 8Ch 8Dh 8Eh 90h 91h 92h 93h 94h 96h 97h 98h 99h 9Ah 9Bh 9Dh 9Fh A0h A1h A2h A3h A4h A6h A8h A9h AAh ABh ADh AEh AFh B0h B1h B2h B3h B4h B6h B8h B9h -
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Silicon Tuner IC
Table 52. THERMOMETER_map Bit TM_ON must be set to logic 1. TM_D[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 53. 200 600 865 IR_MEAS_map IR_MEAS[2:0] 101 110 111 TMVALUE (die temperature) TM_RANGE = 0 60 C 62 C 66 C 64 C 74 C 72 C 68 C 70 C 90 C 88 C 84 C 86 C 76 C 78 C 82 C 80 C TM_RANGE = 1 92 C 94 C 98 C 96 C 106 C 104 C 100 C 102 C 122 C 120 C 116 C 118 C 108 C 110 C 114 C 112 C
fRF(max) (kHz)
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CID_Target_map CID_Target 4 A 1 18 18 A A 18 E 1E 32 3A count_limit 1800 1500 4000
Table 54. fRF(max) 46000 52200 70100 136800 156700 186250 230000 345000 426000 489500 697500 842000
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10. Internal circuitry
Table 55. Symbol FM_IN Internal circuits Pin 8 Description[1] Average DC voltage 0.8 V
8
001aaf836
RF_IN
10
0.8 V
10
001aaf837
CAPRFAGC
12
12
001aaf838
2.8 V
LT
13
0.85 V
13
001aaf839
STO
15
0.85 V
15
001aaf840
CAPREGVCO
17
2.8 V (Normal mode); 0 V (Standby mode)
17
001aaf841
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Silicon Tuner IC
Table 55. Symbol
Internal circuits ...continued Pin 19 Description[1] Average DC voltage 0.5 x VCC
MASTERSYNC
19
001aaf842
CAPFILTVCO
20
1.6 V (Normal mode); 0 V (Standby mode)
20
001aaf843
VT_COARSE
21
21
001aaf844
0.5 x VCC
VT_FINE
22
22
001aaf845
0.5 x VCC
CP_LO
24
0.5 x VCC
24
001aaf846
XTALP
26
1.45 V
26
001aaf847
XTALN
27
1.45 V
27
001aaf848
TDA18271HD_4
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Silicon Tuner IC
Table 55. Symbol FREEZE
Internal circuits ...continued Pin 28 Description[1] Average DC voltage 3.3 V
28
001aaf849
XTOUT_MS
29
high-Z
29
001aaf850
XTOUTP
30
2.4 V
30
001aaf851
XTOUTN
31
2.4 V
31
001aaf852
AS
32
high-Z
32
001aaf853
CP_CAL
34
3.3 V (Normal mode); 0.5 x VCC (Calibration mode)
34
001aaf854
VT_CAL
35
35
001aaf855
3.3 V (Normal mode); 0.5 x VCC (Calibration mode)
TDA18271HD_4
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Silicon Tuner IC
Table 55. Symbol SCL
Internal circuits ...continued Pin 38 Description[1] Average DC voltage high-Z
38
001aaf856
SDA
39
high-Z
39
001aaf857
CAPREG18
40
1.8 V (Normal mode); 2.0 V (Sleep mode)
40
001aaf858
CAPREG28
42
2.8 V (Normal mode); 2.4 V (Sleep mode)
42
001aaf859
IFOUTN
45
1.35 V
45
001aaf860
IFOUTP
46
1.35 V
46
001aaf861
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Silicon Tuner IC
Table 55. Symbol V_IFAGC
Internal circuits ...continued Pin 47
47
001aaf862
Description[1]
Average DC voltage high-Z
VSYNC
51
51
001aaf863
high-Z
CAPREGFILTRF
52
2.8 V (Normal mode); 0 V (Sleep mode)
52
001aaf864
[1]
ESD protection components are not shown.
11. Limiting values
Table 56. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter VCC VI supply voltage input voltage pins SDA and SCL all other pins VCC < 3.3 V VCC > 3.3 V Tstg Tj Vesd storage temperature junction temperature electrostatic discharge voltage HBM: EIA/JESD22-A114 MM: EIA/JESD22-A115 -0.3 -0.3 -40 2000 200 VCC + 0.3 V +3.6 +150 110 V C C V V Conditions Min -0.3 -0.3 Max +3.6 +5.5 Unit V V
[1]
The TDA18271HD withstands the latch-up specifications of JEDEC JESD78A, with the specific recommendation using coupling capacitors on pins RF_IN, LT, STO, XTOUTP and XTOUTN.
12. Thermal characteristics
Table 57. Symbol Rth(j-c)
[1]
Thermal characteristics[1] Parameter thermal resistance from junction to case Conditions according to JEDEC specification Typ 19.6 Unit K/W
The junction temperature can be obtained with the formula Tj = Tamb + Rth(j-a) x VCC x ICC, where Rth(j-a) is the thermal resistance of the application. Rth(j-a) must be such that the resulting Tj does not exceed the maximum value defined in Table 56.
TDA18271HD_4
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Silicon Tuner IC
13. Characteristics
All data in this section refers to Master mode operation
Table 58. Loop-through characteristics (RF input to loop-through output) Tamb = 25 C; VCC = 3.3 V; for test circuit see Figure 27; unless otherwise specified. Symbol fRF(lt) VSWR Gv(lt) Glt NFlt CSO Parameter loop-through RF frequency voltage standing wave ratio loop-through voltage gain loop-through gain variation loop-through noise figure composite second-order distortion composite triple beat bypass isolation from loop-through output to RF input Conditions center of channel loop-through output; 75 nominal impedance 75 load in the RF frequency range; 75 load Standby mode with LT, STO and crystal oscillator on
[1]
Min 45 -
Typ 1.5 3 6.5 -60
Max 864 3 -
Unit MHz
dB dB dB dBc
CTB isol(bp) VL(tun-lto)
[1]
-
-63 24 5
-
dBc dB dBV
leakage voltage in RF TV band between tuner and loop-through output
[1]
Channel loading assumptions: 129 channels (NTSC 129 frequency plan) at 75 dBV.
Table 59. Slave tuner output characteristics (pin STO) Tamb = 25 C; VCC = 3.3 V; for test circuit see Figure 27; unless otherwise specified. Symbol fRF(STO) Zo(STO) Gv(STO) Parameter RF frequency on pin STO output impedance on pin STO voltage gain on pin STO 75 source resistance on RF input; Zi = 35 (75 , VSWR = 2) POWER_LEVEL[6:5] = 00 POWER_LEVEL[6:5] = 01 POWER_LEVEL[6:5] = 10 POWER_LEVEL[6:5] = 11 6 9 12 15 dB dB dB dB Conditions slave tuner output Min 45 30 Typ 35 Max 864 40 Unit MHz
TDA18271HD_4
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Silicon Tuner IC
Table 60. General characteristics for TV reception (RF input to IF output) Tamb = 25 C; VCC = 3.3 V; IF output level option 2 V (p-p); IF output load = 1 k on each terminal; for test circuit see Figure 27; unless otherwise specified. Symbol Supply VCC ICC supply voltage supply current Normal mode Standby mode with LT, STO and crystal oscillator on (default at POR) Standby mode with only crystal oscillator and its output on Device off mode P Tamb Input fRF VSWR NFtun Gv(tun)max RF frequency center of channel 45 1 dB gain compression, one analog TV signal at RF input (-5 dBm) at RF input; in RF band 2 5.5 83 71 103 864 MHz dB dB dB dBV voltage standing RF input; 75 nominal wave ratio impedance tuner noise figure maximum tuner voltage gain maximum gain 2 V (p-p) IF output selection power dissipation ambient temperature 3.13 3.30 180 40 235 51 3.47 290 65 V mA mA Parameter Conditions Min Typ Max Unit
10 1 0
15 2 780 -
20 5 70
mA mA mW C
GAGC(tun) tuner AGC gain range Vi(max) maximum input voltage leakage voltage between tuner and RF
VL(tun-RF)
-
0
-
dBV
Output Vo(IF)dif(p-p) peak-to-peak differential IF output voltage IF_LEVEL[2:0] = 000 IF_LEVEL[2:0] = 001 IF_LEVEL[2:0] = 010 IF_LEVEL[2:0] = 110 IF_LEVEL[2:0] = 111 Zo(IF) GAGC(IF) Gtlt IF output impedance IF AGC GAIN range tilt gain differential mode; magnitude value 2 V (p-p) IF output voltage selection RF frequency range; 6/7/8 MHz channel 2 1.25 1 0.6 0.5 100 30 2 4 V V V V V dB dB
TDA18271HD_4
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Silicon Tuner IC
Table 60. General characteristics for TV reception (RF input to IF output) ...continued Tamb = 25 C; VCC = 3.3 V; IF output level option 2 V (p-p); IF output load = 1 k on each terminal; for test circuit see Figure 27; unless otherwise specified. Symbol fIF(stpb)lp Parameter low-pass stop-band IF frequency Conditions 60 dB attenuation 6 MHz IF filter 7 MHz IF filter 8 MHz IF filter image td(grp) image rejection group delay time analog TV; difference between f1 and f2 in IF Std B; f1 = 1.57 MHz; f2 = 6 MHz Std G; f1 = 2.67 MHz; f2 = 7.1 MHz Std M/N; f1 = 1.82 MHz; f2 = 5.4 MHz tripple ripple time digital TV; difference between f1 and f2 in digital channel ATSC 6 MHz; f1 = 0.75 MHz; f2 = 5.75 MHz DVB-T 6 MHz; f1 = 0.8 MHz and f2 = 5.8 MHz DVB-T 7 MHz; f1 = 0.5 MHz and f2 = 6.5 MHz DVB-T 8 MHz; f1 = 0.5 MHz and f2 = 7.5 MHz QAM 6 MHz; f1 = 1.5 MHz and f2 = 6.5 MHz QAM 8 MHz; f1 = 1.5 MHz and f2 = 8.5 MHz n Various tstartup(tun) tset Sdig Sa tuner start-up time setting time at power-up channel change
2 ); 3 [1]
Min -
Typ 14 16 18 65
Max -
Unit MHz MHz MHz dB
-
130 36 92
-
ns ns ns
-
395 365 478 515 155 180 -89 1.5 20 -82 58
-
ns ns ns ns ns ns dBc/Hz s ms dBm dBV
phase noise
1 kHz and 10 kHz; see Figure 23
digital sensitivity DVB-T (64 QAM BER = 2.10-4 analog sensitivity
50 dB video SNR weighted 22 dBV (color loss)
[2]
[1] [2]
Measured with TDA10048HN channel decoder. Measured with TDA8295 IF modulator.
TDA18271HD_4
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Product data sheet
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TDA18271HD
Silicon Tuner IC
Table 61. General characteristics for FM radio reception (FM input to IF output) VCC = 3.3 V; Tamb = 25 C; IF output load of 1 k on each terminal; for test circuit see Figure 27; unless otherwise specified. Symbol Parameter Supply ICC supply current FM mode with loop-through, slave tuner output and crystal oscillator on (default at POR) 265 315 mA Conditions Min Typ Max Unit
Input fRF VSWR Output fo Vo(p-p) output frequency peak-to-peak output voltage IF IF_LEVEL[2:0] = 000 IF_LEVEL[2:0] = 001 IF_LEVEL[2:0] = 010 IF_LEVEL[2:0] = 111 isol(bp) bypass isolation in FM band between pins RF_IN and pin FM_IN 1 2.0 1.25 1.0 0.5 32 MHz V V V V dB RF frequency voltage standing wave ratio 75 nominal impedance 65 2 108 MHz
Table 62. Characteristics of terminals Tamb = 25 C; VCC = 3.3 V; 2.2 nF on input pin V_IFAGC; for test circuit see Figure 27; unless otherwise specified. Symbol VAGC Zi dGAGC/dV Parameter AGC voltage input impedance rate of change of AGC gain with voltage crystal frequency input impedance magnitude value; master mode 16 MHz output frequency 10 k//10 pF AC load 10 k//10 pF AC load 10 k//10 pF AC load Conditions Min 0 Typ high-Z 30 Max VCC 55 Unit V dB/V IF AGC input: pin V_IFAGC
Crystal oscillator fxtal Zi 15.99 16 500 16.01 MHz
Crystal oscillator output buffer; pins XTOUTP and XTOUTN Ro Vo(p-p) SRr SRf output resistance peak-to-peak output voltage slew rate of rising signal slew rate of falling signal 460 0.4 40 40 V V/s V/s
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Silicon Tuner IC
Table 62. Characteristics of terminals ...continued Tamb = 25 C; VCC = 3.3 V; 2.2 nF on input pin V_IFAGC; for test circuit see Figure 27; unless otherwise specified. Symbol I2C-bus[1] Pin SCL VIL VIH fSCL pin SDA VOH VIL VIH HIGH-level output voltage LOW-level input voltage HIGH-level input voltage ISDA = 3 mA (sink current) fixed input levels VDD related input levels fixed input levels VDD related input levels 3 0.4 1.5 V V V V LOW-level input voltage HIGH-level input voltage SCL clock frequency fixed input levels VDD related input levels fixed input levels VDD related input levels 3 1.5 400 V V V kHz 0.3VDD V Parameter Conditions Min Typ Max Unit
0.7VDD -
0.3VDD V
0.7VDD -
[1]
Devices that use non-standard supply voltages, which do not conform to the intended I2C-bus system levels, must relate their input levels to the supply voltage to which the pull-up resistors are connected.
-70 n (dBc/Hz) -80
(1) (2)
001aah561
-90
-100
(3)
-110
-120 40 140 240 340 440 540 640 740 840 940 fRF (MHz)
(1) Offset is 1 kHz (2) Offset is 10 kHz (3) Offset is 100 kHz
Fig 23. Typical phase noise curve
TDA18271HD_4
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Silicon Tuner IC
0 selectivity (dB) -10 -20 -30
(1) (2) (3) (4) (5)
001aah562
-40 -50 -60 -70
-3
1
5
9
13
17 fIF (MHz)
19
(1) 1.5 MHz bandwidth filter (2) 6 MHz bandwidth filter (3) 7 MHz bandwidth filter (4) 8 MHz bandwidth filter (5) 9 MHz bandwidth filter
Fig 24. Typical IF selectivity curves
TDA18271HD_4
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Product data sheet
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Silicon Tuner IC
14. Application information
14.1 Application examples
V_IFAGC XTAL RF RF SILICON TUNER TV RF SURGE PROTECTION LT IFOUTP IFOUTN CHANNEL DEMODULATOR I2C-bus (gated)
SURGE PROTECTION
TS
TDA18271HD
(MASTER)
TDA10048HN
MASTERSYNC
XTOUTN
XTOUTP
FREEZE
3.3 V V_IFAGC
3.3 V
I2C-bus
STO
1.2 V
I2C-bus (gated)
SILICON TUNER
IFOUTP IFOUTN
TDA18271HD
(SLAVE)
CHANNEL DEMODULATOR
TS
TDA10048HN
3.3 V
3.3 V
I2C-bus
1.2 V
001aah040
Fig 25. Example of DVB-T dual tuner reception for PCTV applications
DVB-T CHANNEL DECODER
MPEG2 transport stream
(TDA1004x)
CB FILTER TV V_IFAGC TUNER FM radio IFOUTN IFOUTP IFOUT VSYNC IF DEMODULATOR CVBS SSIF AUDIO AND VIDEO DECODER WITH PCI INTERFACE
PCI-bus
TDA18271HD
(TDA8295)
(SAA713x)
XTAL
001aag457
Fig 26. Example of hybrid reception for PCTV applications
14.2 Application notes
Application notes are available for the following:
* Analog and digital front end: see application note AN605 * Analog front end: see application note AN602 * Dual tuner application for PCTV: see application note AN604
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Product data sheet Rev. 04 -- 19 May 2009
(c) NXP B.V. 2009. All rights reserved. TDA18271HD_4
15. Test information
NXP Semiconductors
GND GND GND GND GND GND GND GND GND GND GND CAPREGFILTRF VSYNC GND GND
VCC3.3 SDA GND SCL
6 5 4 3 2 1
J1 R1 2.2 k R2 2.2 k
C127 100 nF
C126 2.2 nF R118 150 k J109
VCC3.3 SDA SCL
TP104 VSYNC_M
ST1
V_IFAGC_M
R117 56 J108
C125 100 nF
R116 470 R115 56 R114 470
IFOUTP
VCC3.3
J101 R101 C101 1 nF_5 %
GND
C124
J107
FMIN_M VCC1
C128 47 nF J102 R102 C102 1 nF_5 %
GND GND GND GND GND GND GND FM_IN VCC RF_IN GND CAPRFAGC LT GND STO SP_M VCC
RFIN_M TP101 CAPRFAGC
C103
220 nF J103 C104 1 nF_5 %
LT_M VCC2
C105 47 nF
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 8 41 TDA18271HD 40 9 39 10 11 38 12 37 13 36 35 14 15 34 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND CP_LO CAPREGVCO VCC MASTERSYNC CAPFILTVCO VT_COARSE VT_FINE GND XTALP XTALN FREEZE XTOUT_MS XTOUTP XTOUTN AS
IFOUTN
GND V_IFAGC IFOUTP IFOUTN VCC GND CAPREG28 GND CAPREG18 SDA SDA SCL SCL GND GND VT_CAL CP_CAL VCC
100 nF
VCC2
C123 47 nF C122 100 nF C121 10 nF
VCC2
C117 47 nF R112 390 C118 6.8 nF R113 120 C119 3.9 nF
C116 150 pF R111
J106
VCC3
C108 47 nF
C120 220 nF
C115 4.7 nF
MASTER SYNC
J105
R106
C107 100 nF
C109 100 nF
C114 4.7 nF
XOUTN_M TP103 XOUTP_M XOUTP_M TP102 FREEZE_CMOT FREEZE
TDA18271HD
MASTERSYNC
R107 470 J104 R104 n.c. C106 C110 220 nF R108 390 C111 1 nF C112 6.8 nF C113 33 pF C129
Silicon Tuner IC
SP_M
SP_M
1 nF_5 % R105 39
5.6 pF Y1
C200 33 pF
RFIN_S
16 MHz
001aah560
64 of 70
Fig 27. Test circuit
NXP Semiconductors
TDA18271HD
Silicon Tuner IC
16. Package outline
HLQFN64R; plastic thermal enhanced low profile quad flat package; no leads; 64 terminals; resin based; body 9 x 9 x 1.6 mm
SOT903-1
D terminal 1 index area
B
A
E
A
detail X
e1 L L1
17 16
C 1/2 e b
32 33
e
v w
M M
CAB C
y1 C
y
e Em El En Ek Ej Eh e2 1/2 e
1
48 64 49
terminal 1 index area
Dh Dj Dk Dl Dm 0 2.5 scale 5 mm L1 0.18 0.08 Ej 0.69 0.59 v 0.1
X
w 0.05
y 0.05
y1 0.1
DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.7 b 0.3 0.2 D 9.1 8.9 Dh 2.92 2.82 Dj 0.86 0.76 Dk 3.32 3.22 Dl 1.79 1.69 Dm 2.16 2.06 E 9.1 8.9 Eh 0.31 0.21 Ek 1.79 1.69 El 0.79 0.69 Em 2.63 2.53 En 2.02 1.92 e 0.5 e1 7.5 e2 7.5 L 0.45 0.40
OUTLINE VERSION SOT903-1
REFERENCES IEC --JEDEC --JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 06-03-29 07-11-14
Fig 28. Package outline SOT903-1 (HLQFN64R)
TDA18271HD_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 19 May 2009
65 of 70
NXP Semiconductors
TDA18271HD
Silicon Tuner IC
17. Printed-circuit board
17.1 Reflow profile
See application note AN10366.
17.2 De-soldering recommendation
See application note AN10366.
TDA18271HD_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 19 May 2009
66 of 70
NXP Semiconductors
TDA18271HD
Silicon Tuner IC
17.3 Footprint layout
Hx D P 1/2 P
C
0.065 Vd Vx 0.12 Hy SPy1 SPy Vy1 Vy3 Vy2 SLy SLy1 By Vd1
Ay
SPx SPx2 SPx1 SLx Bx Ax SLx1
solder lands
solder paste
solder resist occupied area
SPy1 0.3
Vd 0.35
Vd1 0.5
Vx 0.8
Vy1 0.9
Vy2 0.8
Vy3 0.9
DIMENSIONS in mm P 0.500 Ax 9.000 Ay 9.000 Bx 7.880 By 7.880 C 0.555 D 0.250 Hx 9.500 Hy 9.500 SLx 4.610 SLx1 1.740 SLy 3.220 SLy1 0.640 SPx 0.800 SPx1 2.065 SPx2 0.3 SPy 0.7
Fig 29. Footprint HLQFN64R (SOT903-1)
TDA18271HD_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 19 May 2009
67 of 70
NXP Semiconductors
TDA18271HD
Silicon Tuner IC
18. Abbreviations
Table 63. Acronym AGC BER CB CP DVB-T DVD-R ESD HBM IF LNA LO LT MM PCTV PLL QAM RoHS SAW SNR TS VCO Abbreviations Description Automatic Gain Control Bit Error Rate Citizens Band Charge Pump Digital Video Broadcasting - Terrestrial Digital Versatile Disk-Recordable ElectroStatic Discharge Human Body Model Intermediate Frequency Low Noise Amplifier Local Oscillator Loop-Through Machine Model Personal Computer TeleVision Phase-Locked Loop Quadrature Amplitude Modulation Restriction of Hazardous Substances Surface Acoustic Wave Signal-to-Noise Ratio Transport Stream Voltage Controlled Oscillator
19. Revision history
Table 64. Revision history Release date 20090519 Data sheet status Product data sheet Change notice Supersedes TDA18271HD_3 Document ID TDA18271HD_4 Modifications: TDA18271HD_3 TDA18271HD_2 TDA18271HD_1
*
Figure 16 "Flowchart TDA18271RFtrackingFiltersCorrection" updated the formula "RFCAL_TCOMP = dCoverdT x (TMVALUE_CURRENT - TMVALUE_RFCAL) / 1000" Product data sheet Product data sheet Product data sheet TDA18271HD_2 TDA18271HD_1 -
20080911 20080306 20070806
TDA18271HD_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 19 May 2009
68 of 70
NXP Semiconductors
TDA18271HD
Silicon Tuner IC
20. Legal information
20.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
20.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. Silicon Tuner -- is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
TDA18271HD_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 19 May 2009
69 of 70
NXP Semiconductors
TDA18271HD
Silicon Tuner IC
22. Contents
1 2 3 3.1 3.2 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.5 9 9.1 9.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 9.3.10 9.3.11 9.3.12 9.3.13 9.3.14 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Target applications . . . . . . . . . . . . . . . . . . . . . . 1 Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 6 TV and FM reception . . . . . . . . . . . . . . . . . . . . 6 Master and slave operation. . . . . . . . . . . . . . . . 6 Tuner outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Loop-through output . . . . . . . . . . . . . . . . . . . . . 7 Slave tuner output. . . . . . . . . . . . . . . . . . . . . . . 7 Crystal input mode . . . . . . . . . . . . . . . . . . . . . . 7 Crystal output mode . . . . . . . . . . . . . . . . . . . . . 7 Control interface . . . . . . . . . . . . . . . . . . . . . . . . 8 I2C-bus format, Write/Read mode . . . . . . . . . . 8 I2C-bus at Power-On Reset . . . . . . . . . . . . . . 11 Description of symbols used in I2C-bus format table. . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C-bus address selection. . . . . . . . . . . . . . . . 13 Description of chip ID byte . . . . . . . . . . . . . . . 14 Description of temperature sensor byte . . . . . 14 Description of power level byte (read mode) . 15 Description of Easy prog byte 1 . . . . . . . . . . . 15 Description of Easy prog byte 2 . . . . . . . . . . . 16 Description of Easy prog byte 3 . . . . . . . . . . . 16 Description of Easy prog byte 4 . . . . . . . . . . . 17 Description of Easy prog byte 5 . . . . . . . . . . . 18 Description of Cal post-divider byte . . . . . . . . 18 Description of Cal divider bytes 1, 2 and 3 . . . 18 Description of Main post-divider byte . . . . . . . 19 Description of Main divider bytes 1, 2 and 3. . 19 Description of Extended bytes 1 to 23 . . . . . . 19 I2C-bus programming flowcharts . . . . . . . . . . 22 Flowchart explanation. . . . . . . . . . . . . . . . . . . 22 Flowchart TDA18271SetRf_dual . . . . . . . . . . 25 Flowchart TDA18271InitCal . . . . . . . . . . . . . . 25 Flowchart TDA18271FixedContentsI2Cupdate 26 Flowchart TDA18271CalcRFFilterCurve . . . . 27 Flowchart TDA18271RFTrackingFiltersInit . . . 29 Flowchart TDA18271PowerScanInit . . . . . . . . 31 9.4.8 9.4.9 9.4.10 9.4.11 9.4.12 9.4.13 9.4.14 9.4.15 9.4.16 9.4.17 9.5 10 11 12 13 14 14.1 14.2 15 16 17 17.1 17.2 17.3 18 19 20 20.1 20.2 20.3 20.4 21 22 Flowchart TDA18271PowerScan . . . . . . . . . . Flowchart TDA18271CalibrateRF . . . . . . . . . Flowchart TDA18271MSPOR . . . . . . . . . . . . Flowchart TDA18271RFTrackingFilters Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . Flowchart TDA18271ChannelConfiguration. . Flowchart TDA18271CalcMAINPLL . . . . . . . . Flowchart TDA18271CalcCALPLL . . . . . . . . . Flowchart TDA18271ThermometerRead . . . . Flowchart TDA18271Read . . . . . . . . . . . . . . . Flowchart TDA18271ReadExtended . . . . . . . Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Application examples . . . . . . . . . . . . . . . . . . . Application notes . . . . . . . . . . . . . . . . . . . . . . Test information. . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Printed-circuit board . . . . . . . . . . . . . . . . . . . . Reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . De-soldering recommendation . . . . . . . . . . . . Footprint layout. . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 33 35 35 37 39 39 40 41 42 43 52 56 56 57 63 63 63 64 65 66 66 66 67 68 68 69 69 69 69 69 69 70
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 May 2009 Document identifier: TDA18271HD_4

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